MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 133

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
BSR rel
CLC
CLI
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Source
Form
Branch to
Subroutine
Clear Carry Bit
Clear Interrupt Mask
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
Compare Index
Register with
Memory Byte
Decrement Byte
EXCLUSIVE OR
Accumulator with
Memory Byte
Increment Byte
Unconditional Jump
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Operation
Table 14-6. Instruction Set Summary (Sheet 3 of 6)
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
M ← ( ) = $FF – (M)
M ← ( ) = $FF – (M)
M ← ( ) = $FF – (M)
PC ← Jump Address
A ← ( ) = $FF – (M)
X ← ( ) = $FF – (M)
PC ← (PC) + rel
SP ← (SP) – 1
A ← (A) ⊕ (M)
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
Description
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
A ← (A) + 1
X ← (X) + 1
M ← $00
M ← $00
M ← $00
M
M
M
A ← $00
X ← $00
(A) – (M)
A
X
(X) – (M)
C ← 0
I ← 0
— — — — —
— — — — 0
— 0 — — —
— — 0 1 —
— —
— —
— —
— —
— —
— —
— — — — —
H
on CCR
I
Effect
N Z C
—
—
—
1
1
Instruction Set Summary
REL
IMM
EXT
IMM
EXT
IMM
EXT
EXT
INH
INH
DIR
INH
INH
DIR
DIR
INH
INH
DIR
DIR
INH
INH
DIR
DIR
INH
INH
DIR
IX1
IX2
IX1
IX1
IX2
IX1
IX1
IX2
IX1
IX1
IX2
IX1
IX
IX
IX
IX
IX
IX
IX
IX
CC
DC
AD
BC
EC
FC
9A
3F
4F
5F
6F
7F
A1
B1
C1
D1
E1
F1
A3
B3
C3
D3
E3
F3
3A
4A
5A
6A
7A
A8
B8
C8
D8
E8
F8
3C
4C
5C
6C
7C
98
33
43
53
63
73
ee ff
ee ff
ee ff
ee ff
hh ll
hh ll
hh ll
hh ll
dd
dd
dd
dd
dd
dd
dd
dd
rr
ff
ff
ff
ff
ff
ff
ff
ff
ii
ii
ii
6
2
2
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
3
2
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