ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 178

no-image

ST10F280

Manufacturer Part Number
ST10F280
Description
MCU 16BIT 512K FLASH MAC 208-PBG
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F280

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, SSC
Peripherals
POR, PWM, WDT
Number Of I /o
143
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
18K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 32x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
208-PBGA
Processor Series
ST10F28x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST10F280
Manufacturer:
ST
0
Part Number:
ST10F280-B3
Manufacturer:
ST
Quantity:
6 221
Part Number:
ST10F280-B3
Manufacturer:
ST
Quantity:
20 000
Part Number:
ST10F280-B3.
Manufacturer:
ST
0
Part Number:
ST10F280-Q3TR
Manufacturer:
SONY
Quantity:
26
Part Number:
ST10F280-Q3TR
Manufacturer:
ST
Quantity:
20 000
ST10F280
Figure 88 : CLKOUT and READY
Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
178/186
CLKOUT
ALE
RD, WR
Synchronous
READY
Asynchronous
READY
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling
point terminates the currently running bus cycle.
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enabled), it must fulfill t
the command (see Note 4)).
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this
delay is zero.
7. The next external bus cycle may start here.
t
t
58
32
3)
t
t
t
59
30
34
Running cycle 1)
37
in order to be safely synchronized. This is guaranteed, if READY is removed in response to
2)
t
t
33
31
t
t
35
58
3)
t
37
3)
t
t
36
59
t
5)
29
t
35
wait state
READY
3)
t
36
MUX / Tri-state 6)
t
60 4)
6)
7)

Related parts for ST10F280