ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 151

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

BUSCON4 (FF1Ah / 8Dh)
Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l1 and l2 of PORT0 latched at the end of the reset sequence.
MCTC
RWDCx
MTTCx
BTYP
ALECTLx
BUSACTx
RDYENx
RDYPOLx
CSRENx
CSWENx
CSWEN4 CSREN4 RDYPOL4 RDYEN4
RW
15
2. BUSCON0 is initialized with 0000h, if EA pin is high during reset. If EA pin is low during reset, bit BUSACT0 and ALECTRL0 are
set (’1’) and bit field BTYP is loaded with the bus configuration selected via PORT0.
RW
14
Memory Cycle Time Control (Number of memory cycle time wait states)
0 0 0 0: 15 wait states (Nber = 15 [MCTC])
. . .
1 1 1 1: No wait states
Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
Memory Tristate Time Control
‘0’: 1 wait state
‘1’: No wait state
External Bus Configuration
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset.
ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see ADDRSEL)
READY Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
Ready Active Level Control
‘0’: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY pin,
‘1’: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on READY pin.
Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
RW
13
RW
12
11
-
BUSACT4
RW
10
SFR
ALECTL4
RW
9
8
-
7
BTYP
RW
6
MTTC4 RWDC4
RW
5
RW
4
Reset Value: 0000h
3
ST10F280
MCTC
2
RW
151/186
1
0