ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 11

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 1 : Ball Description (continued)
P3.0 - P3.13,
P3.15
P4.0 – P4.7
Symbol
Number
M14
M15
M16
Ball
R12
P12
R13
P13
R14
P14
R15
R16
N14
P15
P16
N16
K14
K15
T13
T14
T17
L14
L15
L16
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise program-
mable for input or output via direction bits. For a pin configured as input, the out-
put driver is put into high-impedance state. Port 3 outputs can be configured as
push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL
or special).
The following Port 3 pins also serve for alternate functions:
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.15
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put into
high-impedance state. The input threshold is selectable (TTL or special).
P4.6 & P4.7 outputs can be configured as push-pull or open-drain drivers.
In case of an external bus configuration, Port 4 can be used to output the seg-
ment address lines:
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
T0IN
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
T3IN
T2IN
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
CLKOUT System Clock Output (=CPU Clock)
A16
A17
A18
A19
A20
CAN2_RxD
A21
CAN1_RxD
A22
CAN1_TxD
A23
CAN2_TxD
CAPCOM Timer T0 Count Input
GPT2 Timer T6 Toggle Latch Output
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 External Up / Down Control Input
GPT1 Timer T4 Input for Count / Gate /
Reload / Capture
GPT1 Timer T3 Count / Gate Input
GPT1 Timer T2 Input for Count / Gate /
Reload / Capture
SSC Master-Receive / Slave-Transmit I/O
SSC Master-Transmit / Slave-Receive O/I
ASC0 Clock / Data Output (Asynchronous / Synchronous)
ASC0 Data Input (Asynchronous) or I/O (Synchronous)
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe
SSC Master Clock Output / Slave Clock Input
Least Significant Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
CAN2 Receive Data Input
Segment Address Line
CAN1 Receive Data Input
Segment Address Line, CAN_TxD
CAN1 Transmit Data Output
Most Significant Segment Address Line
CAN2 Transmit Data Output
Function
ST10F280
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