ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 171

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

20.4.11 - Demultiplexed Bus
V
ALE cycle time = 4 TCL + 2t
Table 42 : Demultiplexed Bus Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
5
6
80
81
12
13
14
15
16
17
18
20
21
22
24
26
28
28h
38
39
DD
= 5V
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
CC
CC
SR
ALE high time
Address setup to ALE
Address/Unlatched CS setup to
RD, WR
(with RW-delay)
Address/Unlatched CS setup to
RD, WR
(no RW-delay)
RD, WR low time
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address/Unlatched CS to valid
data in
Data hold after RD
rising edge
Data float after RD rising edge
(with RW-delay)
Data float after RD rising edge
(no RW-delay)
Data valid to WR
Data hold after WR
ALE rising edge after RD, WR
Address/Unlatched CS hold
after RD, WR
Address/Unlatched CS hold
after WRH
ALE falling edge to Latched CS
Latched CS low to Valid Data In
(with RW-delay)
(no RW-delay)
(with RW-delay)
(no RW-delay)
10%, V
SS
Parameter
= 0V, T
A
A
+ t
= -40 to +125°C, C
C
+ t
1 3
1 3
2
F
(50ns at 40MHz CPU clock without wait states).
16.5 + 2t
Minimum
15.5 + t
0 (no t
Maximum CPU Clock
-10 + t
28 + t
10 + t
4 + 2t
(t
-5 + t
-5 + t
4 + t
2 + t
-4 - t
4 + t
F
–
–
–
–
0
–
–
–
> 0)
A
A
F
A
F
F
A
C
C
F
F
= 40MHz
C
)
A
L
= 50pF,
18.5 + t
Maximum
22 + 2t
+ t
18.5 + t
16.5 + t
6 + t
4 + t
6 - t
C
18.5
t
t
–
–
–
–
–
–
–
–
–
–
–
–
C
C
+ 2t
A
C
F
A
A
C
F
A
+
+
2 TCL - 8.5 + 2t
2 TCL - 9.5 + t
3 TCL - 9.5 + t
TCL - 10.5 + t
TCL - 8.5 + 2t
2 TCL - 15 + t
TCL - 8.5 + t
TCL - 8.5 + t
Minimum
0 (no t
-10 + t
(t
-5 + t
-5 + t
-4 - t
F
1/2 TCL = 1 to 40MHz
Variable CPU Clock
–
–
–
–
0
–
–
–
> 0)
A
F
F
F
F
)
A
F
A
A
C
C
C
A
2 TCL - 19 + t
3 TCL - 19 + t
2 TCL - 8.5
+ t
+ t
3 TCL - 19
4 TCL - 28
3 TCL - 19
Maximum
+ 2t
+ t
TCL - 8.5
+ t
F
F
6 - t
C
A
+ 2t
+ 2t
A
–
–
–
–
–
–
–
–
–
–
–
–
+ 2t
+ t
+ t
A
ST10F280
A
A
C
C
A
1
1
C
C
171/186
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns