ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 131

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 67 : Synchronous Warm Reset (Long low pulse on RSTIN)
Notes: 1. RSTIN rising edge to internal latch of PORT0 is 3 CPU
17.3 - Software Reset
The reset sequence can be triggered at any time
using the protected instruction SRST (software
reset).
deliberately within a program, for example to leave
bootstrap loader mode, or upon a hardware trap
that reveals a system failure.
Upon execution of the SRST instruction, the
internal reset sequence (1024 TCL) is started.
The microcontroller behaviour is the same as for a
Short
P0.12...P0.6 bit are latched at the end of the reset
sequence, while P0.5...P0.2 bit are cleared.
17.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during
the initialization or when it is not regularly serviced
during program execution it will overflow and it will
trigger the reset sequence.
(6 TCL) clock cycles if the PLL is bypassed and the
prescaler is on (f
cycles (8 TCL).
2. If during the reset condition (RSTIN low), V
drops below the threshold voltage (about 2.5V for 5V
operation), the asynchronous reset is then immediately
entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of
SYSCON register) was previously set by soft-ware. Bit
BDRSTEN is cleared after reset.
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0
Internal
Reset
Signal
Hardware
This
instruction
4 TCL
CPU
200 A Discharge
reset,
= f
12 TCL
XTAL
/ 2), else it is 4 CPU clock
can
except
be
Internally pulled low
that
Reset Configuration
executed
RPD
1024 TCL
voltage
only
Latching point of PORT0
for system start-up configuration
3
Unlike
watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY,
or if READY is sampled active (low) after the
programmed wait states. When READY is
sampled inactive (high) after the programmed wait
states the running external bus cycle is aborted.
Then the internal reset sequence is started. At the
end of the internal reset sequence (1024 TCL),
only P0.12...P0.6 bit are latched, while previously
latched values of P0.5...P0.2 are cleared.
17.5 - RSTOUT Pin and Bidirectional Reset
The RSTOUT pin is driven active (low level) at the
beginning of any reset sequence (synchronous/
asynchronous hardware, software and watchdog
timer resets). RSTOUT pin stays active low
beyond the end of the initialization routine, until
the
Initialization) is completed.
The Bidirectional Reset function is useful when
external devices require a reset signal but cannot
be connected to RSTOUT pin, because RSTOUT
signal lasts during initialisation. It is, for instance,
the case of external memory running initialization
routine before the execution of EINIT instruction.
Bidirectional reset function is enabled by setting
bit 3 (BDRSTEN) in SYSCON register. It only can
be enabled during the initialization routine, before
EINIT instruction is completed.
2
V
RPD
protected
hardware
> 2.5V Asynchronous Reset not entered.
6 or 8 TCL
1
EINIT
and
software
instruction
resets,
ST10F280
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