ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 172

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Table 42 : Demultiplexed Bus Characteristics
Notes: 1. RW-delay and
172/186
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
41
82
83
46
47
48
49
50
51
53
68
55
57
CC
CC
CC
SR
SR
CC
CC
CC
SR
SR
SR
CC
CC
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
Latched CS hold after RD, WR
Address setup to RdCS, WrCS
(with RW-delay)
Address setup to RdCS, WrCS
(no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
t
A
Parameter
refer to the next following bus cycle.
3
3
14.5 + 2t
Minimum
15.5 + t
-8.5 + t
Maximum CPU Clock
28 + t
10 + t
2 + 2t
2 + t
2 + t
–
–
0
–
–
F
F
A
C
C
= 40MHz
F
C
A
Maximum
16.5 + t
16.5 + t
4 + t
4 + t
–
–
–
–
–
–
–
–
–
C
F
C
F
TCL - 10.5 + 2t
3 TCL - 9.5 + t
2 TCL - 15 + t
TCL - 10.5 + t
TCL - 10.5 + t
2 TCL - 10.5 +
2 TCL - 9.5
Minimum
-8.5 + t
+ t
1/2 TCL = 1 to 40MHz
2t
Variable CPU Clock
–
–
0
–
–
A
C
F
C
F
F
C
A
2 TCL - 8.5 + t
2 TCL - 21 + t
3 TCL - 21 + t
TCL - 8.5 + t
Maximum
–
–
–
–
–
–
–
–
–
F
C
C
F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns