ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 134

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
Figure 70 : External Reset Hardware Circuitry
Table 33 : PORT0 Latched Configuration for the Different Resets
Table 34 : PORT0 bit latched into the different registers after reset
Notes: 1. Not latched from PORT0.
134/186
Internal Logic
X : Pin is sampled
- : Pin is not sampled
Software Reset
Watchdog Reset
Short Hardware Reset
Long Hardware Reset
Power-On Reset
PORT0 bit
BUSCON0
PORT0 bit
SYSCON
RP0H
Name
nber
Sample event
2
2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte.
3. Indirectly depend on PORT0.
4. Bits set if EA pin is 1.
CLKCFG
X
X
X
h7
1
1
1
To Clock Generator
CLKCFG
X
X
X
h6
1
1
1
ST10F280
CLKCFG
X
X
X
h5
X
X
1
1
1
-
-
-
SALSEL SALSEL
RSTOUT
To Port 4 Logic
X
X
RSTIN
X
X
X
-
-
-
h4
RPD
1
1
1
X
X
-
-
-
X
X
h3
-
1
1
V
+
DD
X
X
X
X
X
CSSEL
ACT0
R0
V
BUS
X
X
To Port 6 Logic
h2
C0
DD
1
1
4
R2
X
X
X
X
X
BYTDIS
CSSEL
CTL0
ALE
X
h1
Open Drain Inverter
1
X
X
X
X
X
4
3
Hardware
D2
External
WRC
X
X
X
h0
-
1
1
1
X
X
X
X
X
WRCFG
BUSTYP
CLKCFG
BTYP
External
Reset Source
X
I7
PORT0
X
X
X
X
X
1
3
BUSTYP
CLKCFG CLKCFG SALSEL SALSEL
X
X
X
X
X
BTYP
X
X
I6
1
1
D1
X
X
X
X
X
V
+
X
X
X
I5
R
DD
1
1
1
R1
X
X
X
-
-
C1
Internal
BSL
X
X
I4
1
1
X
X
X
-
-
X
X
X
I3
R
X
X
X
1
1
1
-
-
CSSEL CSSEL
X
X
X
X
X
X
I2
R
-
-
1
1
1
Internal Internal
ADP
X
X
X
X
X
I1
-
-
1
1
WRC
EMU
X
X
X
X
X
-
-
I0
1
1