ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 118

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ST10F280

Manufacturer Part Number
ST10F280
Description
MCU 16BIT 512K FLASH MAC 208-PBG
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet

Specifications of ST10F280

Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, SSC
Peripherals
POR, PWM, WDT
Number Of I /o
143
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
18K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 32x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
208-PBGA
Processor Series
ST10F28x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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ST10F280
15 - CAN MODULES
The two integrated CAN modules (CAN1 and
CAN2) are identical and handle the completely
autonomous transmission and reception of CAN
frames in accordance with the CAN specification
V2.0 part B (active) i.e. the on-chip CAN module
can receive and transmit standard frames with
11-bit identifiers as well as extended frames with
29-bit identifiers.
Because of duplication of CAN controllers, the fol-
lowing adjustements are to be considered:
– The same internal register addresses both CAN
– The CAN1 transmit line (CAN1_TxD) is the alter-
– The CAN2 transmit line (CAN2_TxD) is the alter-
– Interrupt of CAN2 is connected to the XBUS in-
– Because of the new XPERCON register, both
– After reset, the CAN1 is selected with the related
15.1 - Memory Mapping
15.1.1 - CAN1
Address range 00’EF00h 00’EFFFh is reserved
for the CAN1 Module access. The CAN1 is
enabled by setting bit 0 of the new XPERCON
register before setting XPEN bit 2 of the SYSCON
register. Accesses to the CAN Module use demul-
tiplexed addresses and a 16-bit data bus (byte
accesses are possible). Two waitstates give an
access time of 100 ns at 40MHz CPU clock. No
tristate waitstate is used.
15.1.2 - CAN2
Address range 00’EE00h 00’EEFFh is reserved
for the CAN2 Module access. The CAN2 is
enabled by setting XPEN bit 2 of the SYSCON
register and bit 1 of the new XPERCON register.
Accesses to the CAN Module use demultiplexed
addresses and a 16-bit data bus (byte accesses
are possible). Two waitstates give an access time
of 100 ns at 40MHz CPU clock. No tristate wait-
state is used.
118/186
controllers, but with the base addresses differing
in address bit A8 and separate chip select for
each CAN module. For address mapping, see
Chapter 4.
nate function of the port P4.6 and the receive
line (CAN1_RxD) is P4.5.
nate function of the port P4.7 and the receive
line (CAN2_RxD) is the alternate function of the
port P4.4.
terrupt line XP1 (CAN1 is on XP0).
CAN modules have to be selected, before the bit
XPEN is set in SYSCON register.
control bit in the XPERCON register. The CAN2
is not selected.
Note: If one or the two CAN modules are used,
15.2 - CAN Bus Configurations
Depending on application, CAN bus configuration
may be one single bus with a single or multiple
interfaces or a multiple bus with a single or
multiple interfaces. The ST10F280 is able to
support these 2 cases.
Single CAN Bus
The
configuration may be implemented using 2 CAN
transceives as shown in Figure 59.
Figure 59 : Single CAN Bus Multiple Interfaces -
Multiple Transceivers
The ST10F280 also supports single CAN Bus
multiple (dual) interfaces using the open drain
option of the CANx_TxD output as shown in Fig-
ure 60. Thanks to the OR-Wired Connection, only
one transceiver is required. In this case the design
of the application must take in account the wire
length and the noise environment.
Figure 60 : Single CAN Bus Dual Interfaces -
Single Transceiver
CAN_H
CAN_H
* Open drain output
single
Port 4 can not be programmed to output all
8 segment address lines. Thus, only 4
segment address lines can be used,
reducing the external memory space to
5M Bytes (1M Byte per CS line).
CAN_H
CAN_H
Transceiver
RxD TxD
CAN1
CAN
Transceiver
RxD TxD
CAN
CAN1
CAN
*
CAN bus
RxD TxD
Bus
CAN bus
CAN2
Transceiver
RxD TxD
CAN2
multiple
*
CAN
2.7k
interfaces
+5V

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