ST10F280 STMicroelectronics, ST10F280 Datasheet - Page 108

• Manufacturer Part Number: ST10F280
• Description: MCU 16BIT 512K FLASH MAC 208-PBG
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F280

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, SSC
• Peripherals: POR, PWM, WDT
• Number Of I /o: 143
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 18K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 32x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-PBGA
• Processor Series: ST10F28x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F280
13.3.2 - Register Description
13.3.2.1 - TCR : Timer Control Register
XTCR (C000h)
108/186
TEN
TUD
TLE
TCS
TIE
TCM
TFP[3:0] Timer Frequency Prescaler
15
R
0
Bit
14
R
0
Timer Enable
When TEN = ’0’, the Timer is disabled (reset value). To avoid glitches, it is recommended to modify TCR in
2 steps, first with new values and and second by setting TEN.
Timer Up / Down Counting
When TUD = ’0’, the Timer is counting "down" (reset value), ie the TCVR (’current value’) register content
is decremented.
When TUD = ’1’, the Timer is counting "up", ie the TCVR (’current value’) register content is incremented.
Timer Load Enable
When the counter has reached its end value (TCVR = TEVR), TCVR is (re)loaded with TSVR (’start value’)
register content when TLE = ’1’. When TLE = ’0’ (reset value), the next state of TCVR depends on TCS
bit.
Timer Continue / Stop
When TLE = ’0’ (no load) and when the counter has reached its end value (TCVR = TEVR), the TCVR
content continues to increment / decrement according to TUD bit when TCS = ’1’ (continue mode).
When TCS = ’0’ (stop mode reset value), TCVR is stopped and its content is frozen.
Timer Output Enable
When the counter has reached its end value (TCVR = TEVR), the XADCINJ output is set when TIE = ’1’.
When TIE = ’0’ (reset value), XADCINJ output is disabled (= ’0’).
Timer Clock Mode Must be Cleared
TCM = ’0’ (reset value), the TCVR clock is derived from internal XCLK clock according to TFP bits.
When TCM = ’0’ (internal clock), the TCVR register clock is derived from the XCLK clock input by dividing
XCLK by 2**(2+ TFP). The coding is as follows :
- 0000 : prescaler by 2 (reset value), XCLK divided by 4
- 0001 : prescaler by 4, XCLK divided by 8
- 0010 : prescaler by 8, XCLK divided by 16
- ...
- 1111 : prescaler by 2**16, XCLK divided by 2**17
13
R
0
12
R
0
11
R
0
10
R
0
9
8
TFP[3:0]
RW
Function
7
6
TCM
RW
5
RW
TIE
4
TCS
RW
3
Reset Value: 0000h
TLE
RW
2
TUD
RW
1
TEN
RW
0