ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 92

• Manufacturer Part Number: ATXMEGA16A4-CUR
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.11
7.11.1
7.11.2
7.11.3
8077H–AVR–12/09
Register Description - DFLL32M/DFLL2M
CTRL - DFLL Control Register
CALA - Calibration Register A
CALB - Calibration Register B
• Bit 7:1 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0 - ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator
CALA and CALB register holds the 13 bit DFLL calibration value that is used for automatic run-
time calibration the internal oscillator. When the DFLL is disabled, the calibration registers can
be written by software for manual run-time calibration of the oscillator. The oscillators will be cal-
ibrated according to the calibration value in these registers also when the DFLL is disabled.
• Bit 7:0 - CALL[7:0]: DFLL Calibration bits
These bits hold the 7 Least Significant Bits (LSB) of the calibration value for the oscillator. After
reset CALL is set to its middle value, and during automatic runtime calibration of the oscillator
these bits are use to change the oscillator frequency. The bits are controlled by the DFLL when
the DFLL is enabled.
• Bit 7:4 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
R
7
R
0
7
–
0
R
7
–
0
R
6
R
1
6
–
0
R
6
–
0
R/W
5
–
R
0
5
0
R
5
–
0
R/W
R/W
R
4
0
4
–
0
4
x
CALL[7:0]
R/W
R/W
R
3
0
3
–
0
3
x
CALH[12:8]
R/W
R/W
R
2
–
0
2
0
2
x
R/W
R/W
R
1
–
0
1
0
1
x
XMEGA A
ENABLE
R/W
R/W
R/W
0
0
0
0
0
x
CTRL
CALA
CALB
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