ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 430

MCU AVR 16+4KB FLASH 49VFBGA

ATXMEGA16A4-CUR

Manufacturer Part Number
ATXMEGA16A4-CUR
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA16A4-CUR

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA16A4-CUR
Manufacturer:
Atmel
Quantity:
10 000
34.3
34.4
34.5
8077H–AVR–12/09
8077F – 02/09
8077E – 01/09
8077D – 12/08
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Added ADC section
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Updated data sheet cross-references.
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Updated
Added ADC section
Added DAC section
Updated the front page.
Updated Feature list in
Updated
20.
Added Signtaure Row register description in Memory section, updated signature row summary
with byte addresses.
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Updated lication of BODACT fuse bits in FUSEBYTE5 in
Fuses and Lockbits” on page
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Updated Overview in
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Inserted a new section
Updated title of the
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”STATUS: Battery Backup Status Register” on page
Table 9-2 on page
”Conversion Result” on page
”Overview” on page
”Capture Channel” on page
Figure 9-5
”Capture Channel” on page
”Production Signature Row” on page 20
”MCUCR – MCU Control Register” on page
”Interrupt Vector Summary - NVM Controller” on page
”Priority Between Channels” on page
”Manually Generating Events” on page 67
”Quadrature Decoder (QDEC)” on page
Figure 13-1 ”General I/O pin functionality.” on page
Table 13-7 ”Event Channel 0 output configurations” on page
Figure 13-10 ”Port override signals and related logic” on page
Table 13-7 on page
External reset characteristics in
”DAC Output model” on page
”Interrupt vector Summary” on page
”ADC Input Model” on page
”Event System” on page
”Memories” on page
”Battery Backup System” on page
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145: Event Channel 0 Output Configurations.
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and inserted
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and
Section 9.4.3 ”External reset” on page
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”Event Routing Network” on page
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Section 4.22 ”Register Summary -
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”User Signature Row” on page
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XMEGA A
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