ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 283

• Manufacturer Part Number: ATXMEGA16A4-CUR
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.11.6
8077H–AVR–12/09
SDRAMCTRLC - SDRAM Control Register C
• Bit 7:6 - WRDLY[1:0]: SDRAM Write Recovery Delay
These bits select the Write Recovery time in number of Peripheral 2x clock (CLK
according to
Table 24-14. SDRAM Write Recovery Delay settings
• Bit 5:3 - ESRDLY[2:0]: SDRAM Exit Self Refresh to Active Delay
This field defines the delay between CKE set high and an Activate command in a number of
Peripheral 2x clock (CLK
Table 24-15. SDRAM Exit Self Refresh Delay settings
• Bit 2:0 - ROWCOLDLY[2:0]: SDRAM Row to Column Delay
This field defines the delay between an Activate command and a Read/Write command as a
number of Peripheral 2x clock (CLK
Table 24-16. SDRAM Row Column Delay settings
Bit
+0x09
Read/Write
Initial Value
ROWCOLDLY[2:0]
ESRDLY[2:0]
WRDLY[1:0]
000
001
010
011
100
101
110
111
000
001
010
011
00
01
10
11
Table 24-11 on page
R/W
7
0
WRDLY[1:0]
R/W
6
0
Group Configuration
0CLK
1CLK
2CLK
3CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
4CLK
5CLK
6CLK
7CLK
Group Configuration
0CLK
1CLK
2CLK
3CLK
PER2
) cycles, according to
R/W
5
0
282.
PER2
ESRDLY[1:0]
R/W
) cycles, according to
4
0
Description
0 CLK
1 CLK
2 CLK
3 CLK
Description
0 CLK
1 CLK
2 CLK
3 CLK
4 CLK
5 CLK
6 CLK
7 CLK
Description
0 CLK
1 CLK
2 CLK
3 CLK
R/W
3
0
Table 24-15 on page
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
PER2
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
cycles delay
R/W
2
0
ROWCOLDLY[1:0]
Table 24-16 on page
R/W
1
0
283.
R/W
0
0
XMEGA A
SDRAMCTRLC
PER2
283.
) cycles,
283