ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 222

• Manufacturer Part Number: ATXMEGA16A4-CUR
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.9.6
19.9.7
8077H–AVR–12/09
ADDR - TWI Master Address Register
DATA -TWI Master Data Register
When the Address (ADDR) register is written with a slave address and the R/W-bit while the bus
is idle, a START condition is issued, and the 7-bit slave address and the R/W-bit are transmitted
on the bus. If the bus is already owned when ADDR is written, a Repeated START is issued. If
the previous transaction was a Master Read and no acknowledge is sent yet, the Acknowledge
Action is sent before the Repeated START condition.
After completing the operation and the acknowledge bit from the slave is received, the SCL line
is forced low if arbitration was not lost. The WIF is set.
If the Bus State is unknown when ADDR is written. The WIF is set, and the BUSERR flag is set.
All TWI master flags are automatically cleared when ADDR is written. This includes BUSERR,
ARBLOST, RIF, and WIF. The Master ADDR can be read at any time without interfering with
ongoing bus activity.
The data (DATA) register is used when transmitting and receiving data. During data transfer,
data is shifted from/to the DATA register and to/from the bus. This implies that the DATA register
cannot be accessed during byte transfers, and this is protected in hardware. The Data register
can only be accessed when the SCL line is held low by the master, i.e. when CLKHOLD is set.
In Master Write mode, writing the DATA register will trigger a data byte transfer, followed by the
master receiving the acknowledge bit from the slave. The WIF and the CLKHOLD flag are set.
In Master Read mode the RIF and the CLKHOLD flag are set when one byte is received in the
DATA register. If Smart Mode is enabled, reading the DATA register will trigger the bus opera-
tion as set by the ACKACT bit. If a bus error occurs during reception the WIF and BUSERR flag
are set instead of the RIF.
Accessing the DATA register will clear the master interrupt flags and the CLKHOLD flag.
Bit
+0x05
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
ADDR[7:0]
DATA[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
XMEGA A
R/W
R/W
0
0
0
0
ADDR
DATA
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