ATXMEGA16A4-CUR Atmel, ATXMEGA16A4-CUR Datasheet - Page 207

• Manufacturer Part Number: ATXMEGA16A4-CUR
• Description: MCU AVR 16+4KB FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA16A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.1
19.3.2
8077H–AVR–12/09
Electrical Characteristics
START and STOP Conditions
Figure 19-2. Basic TWI Transaction Diagram Topology
The master provides the clock signal for the transaction, but a device connected to the bus is
allowed to stretch the low level period of the clock to decrease the clock speed.
The TWI in XMEGA follows the electrical specifications and timing of I
specifications are not 100% compliant so to ensure correct behavior the inactive bus timeout
period should be set in TWI master mode.
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a
transaction. The master issues a START condition(S) by indicating a high to low transition on the
SDA line while the SCL line is kept high. The master completes the transaction by issuing a
STOP condition (P), indicated by a low to high transition on the SDA line while SCL line is kept
high.
Figure 19-3. START and STOP Conditions
Multiple START conditions can be issued during a single transaction. A START condition not
directly following a STOP condition, are named a Repeated START condition (Sr).
SDA
SCL
SDA
SCL
S
The slave provides data on the bus
The master provides data on the bus
The master or slave can provide data on the bus
S
Condition
START
ADDRESS
ADDRESS
S
6 ... 0
Address Packet
R/W
R/W
A
Direction
ACK
Transaction
Data Packet #0
DATA
DATA
7 ... 0
ACK
A
Data Packet #1
DATA
7 ... 0
DATA
2
C and SMBus. These
ACK/NACK
XMEGA A
Condition
A/A
STOP
P
P
P
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