EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 720

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

23
23-8
Synchronous Serial Port
EP93xx User’s Guide
23.5.9 Motorola SPI Format with SPO=1, SPH=0
SFRMOUT /
SCLKOUT /
SFRMIN
Single and continuous transmission signal sequences for Motorola SPI format with SPO=1,
SPH=0 are shown in
In this configuration, during idle periods
SCLKIN
SSPRXD
SSPTXD
Note: In
SSPOE
• the SCLKOUT signal is forced HIGH
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
SSPOE (=0)
SFRMOUT /
SCLKOUT /
the SCLKOUT pad (active LOW enable)
the SCLKOUT pad (active LOW enable).
SSPTXD /
SSPRXD
SCLKIN
SFRMIN
Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
Figure
Figure 23-7. Motorola SPI Frame Format (Continuous Transfer)
23-6, Q is an undefined signal.
LS B
MS B
MS B
Figure 23-6
Copyright 2007 Cirrus Logic
MS B
with SPO=1 and SPH=0
and
Figure
4 t o 16 bi t s
4 t o 16 bi t s
23-7.
LSB
MS B
LS B
LS B
DS785UM1
Q