EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 587

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

UART3LowPwrCntr
UART3DMACtrl
DS785UM1
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
TIS:
RIS:
MIS:
0x808E_0020 - Read/Write
0x0000_0000
UART3 IrDA Low Power Divisor Register. This register is present in UART3
but is not supported.
RSVD:
0x808E_0028 - Read/Write
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
RSVD
25
9
25
9
Transmit Interrupt Status. This bit is set to 1 if the
UARTTXINTR transmit interrupt is asserted, which occurs
when the transmit FIFO is not full. It is set to 0 when the
transmit FIFO is full.
Receive Interrupt Status. This bit is set to 1 if the
UARTRXINTR receive interrupt is asserted, which occurs
when the receive FIFO is not empty. It is set to 0 when the
receive FIFIO is empty.
Modem Interrupt Status. This bit is set to 1 if the
UARTMSINTR modem status interrupt is asserted. This
bit is cleared by writing any value to this register.
Reserved. Unknown During Read.
24
8
24
8
RSVD
RSVD
RSVD
23
7
23
7
22
6
22
6
21
5
21
5
20
4
20
4
UART3 With HDLC Encoder
19
3
19
3
DMAERR
EP93xx User’s Guide
18
2
18
2
TXDMAE
17
17
1
1
RXDMAE
16-11
16
16
0
0
16