EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 687

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

I2SGlCtrl
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
The I
The I
for the data registers can be written without the I
clock cycles when writing to any of the control status registers.
When the I
this register.
The I
0. This will allow data be sent in a loop fashion from the transmitter back through the receiver.
This applies to all channels, with TX1 looped to RX1, and TX2 looped to RX2. When
loopback is active, data at the receiver input is ignored and transmit data is sent out normally.
The transmit section will control the clock configuration during loopback the same as if full-
duplex operation was used.
30
14
2
2
2
S global register deals with enabling the block and whether loopback mode is used.
S enable bit determines whether the PCLK is turned on for the I
S controller loopback mode bit determines if TX channel 0 is connected to RX channel
29
13
2
S controller is required to transmit or receive data, PCLK must be turned on via
28
12
rx2_fifo_empty:
rx2_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
0x8082_000C - Read/Write
0x0000_0000
I
RSVD:
i2s_ife:
i2s_loopback:
2
S Global Control Register
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
RSVD
when = 1, FIFO is empty, otherwise not empty
Reserved. Unknown During Read.
Defines if I
for the I
0 - PCLK is off.
1 - PCLK is on.
Defines loopback operation.
0 - not in loopback mode
1 - Loopback mode selected.
24
8
RSVD
2
S controller.
23
7
2
S controller is enabled and PCLK is turned on
2
S PCLK enabled. The ARM provides its own
22
6
21
5
20
4
19
3
2
S. All registers except
18
2
EP93xx User’s Guide
i2s_loopback
17
I
1
2
S Controller
i2s_ife
21-31
16
0
21