EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 613

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
17.5.2 Functional Description
17.5.2.1 Baud Rate Generation
signalled. The CRC computation logic is preset to all ones before reception/transmission of
each frame and the result is inverted before it used for comparison or transmission. Note that
unlike the address, control and data fields, the 32 bit inverted CRC value is transmitted and
received from least significant byte to most significant and within each byte the least
significant nibble is encoded/decoded first. The cyclical redundancy checker uses the 32
term polynomial:
CRC(x) =
Following reset, the FIR is disabled. Reset also causes the transmit and receive buffers and
tail register to be flushed (buffers marked as empty). To transmit data in FIR mode, use the
following procedure:
The baud rate is derived by dividing down a fixed 48 MHz clock. The 8 MHz baud (time-slot)
clock for the receiver is synchronized with the 4 PPM data stream each time a transition is
detected on the receive data line using a digital PLL. To encode a 4.0 Mbps data stream, the
required “symbol” frequency is 2.0 MHz, with four chips per symbol at a frequency of
8.0 MHz. Receive data is sampled half way through each time-slot period by counting three
out of the six 48 MHz clock periods which make up each chip. Refer to
page
preamble consists of four symbols repeated sixteen times. This repeating pattern is used to
identify the first time-slot or beginning of a symbol and resets the two bit chip counter logic,
such that the 4 PPM data is properly decoded.
1. Set the EN bits in the IrEnable register to 11b for FIR mode. Do not begin data
2. Before enabling the FIR, the user must first clear any writable or “sticky” status bits that
3. Next, the desired mode of operation is programmed in the control register. Set the TXE
4. Write 1 to 3 bytes to the appropriate IrDataTail register.
5. Once the FIR is enabled, transmission/reception of data can begin on the transmit and
(x
transmission.
are set by writing a one to each bit. (A sticky bit is a readable status bit that may be
cleared by writing a one to its location.) Set the TAB and TFC bits in the FISR register,
then read the FISR register to clear all interrupts.
and RXE bits in the IrCtrl register.
receive pins.
32
17-15. The symbols are synchronized during preamble reception. Recall that the
+ x
26
+ x
23
+ x
22
+ x
16
Copyright 2007 Cirrus Logic
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
Figure 17-3 on
+ x + 1)
EP93xx User’s Guide
17-17
IrDA
17