EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 203

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
To minimize these type of spatial interference patterns, it is better to mix up the pattern
sequence similar to that shown in
pixels with sets of every other pixel. Depending on the display and patterns displayed, this
may create another type of apparent image distortion referred to as a walking pattern. One of
the matrix indices may need to be changed to count by 3 to eliminate this combination of
temporal and spatial distortion.
Figure 7-5. Sample Matrix That Avoids Flickering
Frame 00
Frame 10
Frame 0
Frame 2
Figure 7-4. Sample Matrix Causing Flickering
V
E
R
T
V
E
R
T
00
01
11
10
Copyright 2007 Cirrus Logic
Figure
H O R Z
H
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
Raster Engine With Analog/LCD Integrated Timing and Interface
O
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
7-5. Note that the pattern mixes sets of two adjacent
R
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Z
1
1
0
0
1
0
0
0
0
1
Frame 01
Frame 11
Frame 1
Frame 3
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
EP93xx User’s Guide
7-21
7