EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 275

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
8.5.2.2 8 BPP Word Layout
8.5.2.3 16 BPP WORD Layout
For a Block Copy where 4 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
starts at bit 24, etc. The start pixel, P2, is in the word at address 0x0000 and has a beginning
bit position of 16. This makes 16 = 0x10 the value that is used for the SPEL field in the
“SRCPIXELSTRT”
Let the starting SDRAM address of the destination image be 0x0030.
Pixel 2 starts at bit 16, Pixel 3 starts at bit 34, etc. The start pixel, P2, is in the word at address
0x0030 and has a beginning bit position of 16. This makes 16 = 0x10 the value that is used
for the SPEL field in the
The end pixel, P5, is in the word at address 0x0034 and has a beginning bit position of 8. This
makes 8 = 0x8 the value that is used for the EPEL field in the
For a Block Copy where 8 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
starts at bit 16, etc. The start pixel, P0, is in the word at address 0x0000 and has a beginning
bit position of 0. This makes 0 = 0x0 the value that is used for the SPEL field in the
“SRCPIXELSTRT”
Note:The word count for this example would be: 2 - 1 = 1 words, since P5 ends in the 2nd word.
Address
Address
Address
0x000C
0x0000
0x0004
0x0030
0x0034
0x0000
0x0004
0x0008
So, WIDTH = 0x1 would be written to the
31
31
31
Table 8-16. 8 BPP Memory Layout for Destination Image
register.
register.
Table 8-17. 16 BPP Memory Layout for Source Image
Table 8-15. 8 BPP Memory Layout for Source Image
P3
P7
P3
P7
“DESTPIXELSTRT”
24 23
24 23
P1
P3
P5
P7
Copyright 2007 Cirrus Logic
P2
P6
P2
P6
Table 8-15
Table 8-17
“BLKDESTWIDTH”
register.
16 15
16 15
16 15
shows that Pixel 2 starts at bit 16, Pixel 3
shows that Pixel 0 starts at bit 0, Pixel 1
P1
P5
P1
P5
“DESTPIXELSTRT”
register.
8 7
8 7
P0
P2
P4
P6
Table 8-16
P0
P4
P0
P4
Graphics Accelerator
EP93xx User’s Guide
0
0
0
shows that
register.
8-11
8