EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 347

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
Soft Reset:
Definition:
Bit Descriptions:
0x0000_0000
Transmit Control Register.
RSVD:
DefDis:
MBE:
ICRC:
TxPD:
OColl:
SP:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
2-part DefDis. Before a transmission can begin, the MAC
follows a deferral procedure. With the 2-part DefDis bit
clear, the deferral is the standard two-part deferral as
defined in ISO/IEC 8802-3 paragraph 4.2.3.2.1. With the
2-part DefDis bit set, the two-part deferral is disabled. See
Transmit Back-Off paragraph.
ModBackoff Enable. When clear, the ISO/IEC standard
backoff algorithm is used. When set, the Modified Backoff
algorithm is used, which delays longer after each of the
first three Tx collisions.
Inhibit CRC. When this bit is set, there will be no CRC
appended to transmit frames. If the Abort Frame bit is set
in the transmit descriptor for a frame, the frame will be
terminated with a bad CRC.
Tx Pad Disable. When this bit is set, the MAC will not pad
the frame to the legal minimum size (64 bytes). If clear, the
MAC will pad the frame to the minimum legal frame size if
the supplied length is less than 64 bytes. The padded
characters will be the last supplied character in the frame,
repeated.
One Collision. When this bit is set, no attempt is made to
resend frames in the event of a collision.
Send Pause. When set by the host, this bit causes a
pause frame to be transmitted at the earliest opportunity.
This is at the end of the current frame, if one is already in
progress. This bit will remain set until the transmission of
the frame has started. The pause frame is comprised of
the following elements:
Destination Address
Source Address
Type Field
Opcode
Pause Time
Pad fill
1/10/100 Mbps Ethernet LAN Controller
Individual Address number 6
Individual Address number 1
Type Field defined in the
0x0001
Pause Field defined in the
Flow Control Format register0
Flow Control Format register
EP93xx User’s Guide
9-45
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