EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 387

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

RXBufThrshld
DS785UM1
31
15
Definition:
Bit Descriptions:
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
Note: There are other reasons to schedule bus transfers other than reaching the threshold. One
30
14
of these is when an end of frame is received. The lower 2 bits of each threshold are always
zero.
29
13
RSVD
RSVD
28
12
Transmit Status Queue Current Address. The Transmit Status Queue Current
Address contains the address being used to transfer transmit status to the
queue. This register is available for debugging.
TSQCA:
0x8001_00D0 - Read/Write
0x0080_0040
0x0000_0000
Unchanged
Receive Buffer Threshold register. The receive buffer thresholds are used to
set a limit on the amount of receive data which is held in the receive data FIFO
before a bus request will be scheduled. When the number of words in the
FIFO exceeds the threshold value, the Descriptor Processor will schedule a
bus request to transfer data. The actual posting of the bus request may be
delayed due to lack of resources in the MAC, such as no active receive
descriptor.
RSVD:
0:
RDHT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Transmit Status Queue Current Address.
Reserved. Unknown During Read.
Must be written as “0”.
Receive Data Hard Threshold.
24
8
23
7
22
6
RDHT
RDST
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
0
1
0
16
9-85
0
0
0
9