EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 700

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

22
AC97SRx
22-12
AC’97 Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
TX1:
TEN:
AC97SR1 - 0x8088_000C - Read Only
AC97SR2 - 0x8088_002C - Read Only
AC97SR3 - 0x8088_004C - Read Only
AC97SR4 - 0x8088_006C - Read Only
Status Registers. The AC’97 Controller status registers are read only registers
that give information about the transmit/receive status of the block. After reset,
the TXFF, RXFF and TXBUSY are “0”, and TXFE and RXFE are “1”.
RSVD:
TXUE:
RXOE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
FIFO contains SLOT1 data (only use if sampling rate is
48 kHz). Takes precedence over AC97S1DATA.
A “1” written to this bit enables the transmit for this FIFO
and enables the PCLK for the respective Channel.
Reserved. Unknown During Read.
TX Underrun Error - This bit is set to “1” if an underrun
error has been detected (if data is to be transmitted and
the FIFO is empty).
This bit is cleared to “0” by writing to the AC97DR register.
Note: Bit will only be set if FIFO had been written to at least once in
current data transfer.
RX Overrun Error - This bit is set to “1” if an overrun error
has been detected. This bit is set to “1” if data is received
and the FIFO is already full.
This bit is cleared to “0” by reading the AC97DR register.
24
8
RSVD
23
7
TXUE
22
6
RXOE
21
5
TXBUSY
20
4
TXFF
19
3
RXFF
18
2
TXFE
17
1
DS785UM1
RXFE
16
0