PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet - Page 261

• Manufacturer Part Number: PIC18C658-I/L
• Description: IC PIC MCU OTP 16KX16 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/L

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Number Of I /o: 52
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFPAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658IL; Q1162292

23.0
The PIC18CXX8 instruction set adds many enhance-
ments to the previous PICmicro
maintaining an easy migration from these PICmicro
instruction sets.
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The
Table 23-2 lists byte-oriented, bit-oriented, literal
and control operations. Table 23-1 shows the opcode
field descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
'f' represents a file register designator and 'd' repre-
sents a destination designator. The file register desig-
nator specifies which file register is to be used by the
instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the WREG register. If 'd' is one, the result is
placed in the file register specified in the instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
'b' represents a bit field designator which selects the
number of the bit affected by the operation, while 'f' rep-
resents the number of the file in which the bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
• The desired FSR register to load the literal value
• No operand required
(specified by the value of ’k’)
into (specified by the value of ’f’)
(specified by the value of ’—’)
2000 Microchip Technology Inc.
The file register (specified by the value of ’f’)
The destination of the result
(specified by the value of ’d’)
The accessed memory
(specified by the value of ’a’)
The file register (specified by the value of ’f’)
The bit in the file register
(specified by the value of ’b’)
The accessed memory
(specified by the value of ’a’)
PIC18CXX8
INSTRUCTION SET SUMMARY
instruction
®
instruction sets, while
set
summary
Advanced Information
in
The control instructions may use some of the following
operands:
• A program memory address (specified by the
• The mode of the Call or Return instructions (spec-
• The mode of the Table Read and Table Write
• No operand required
All instructions are a single word, except for four double
word instructions. These three instructions were made
double word instructions so that all the required infor-
mation is available in these 32-bits. In the second word,
the 4-MSb’s are 1’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 s. Two
word branch instructions (if true) would take 3 s.
Figure 23-1 shows the general formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
where h signifies a hexadecimal digit.
The Instruction Set Summary, shown in Table 23-2,
lists the instructions recognized by the Microchip
assembler (MPASM
Section 23.1 provides a description of each instruction.
value of ’n’)
ified by the value of ’s’)
instructions (specified by the value of ’m’)
(specified by the value of ’—’)
0xhh
TM
).
PIC18CXX8
DS30475A-page 261