PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet - Page 175

• Manufacturer Part Number: PIC18C658-I/L
• Description: IC PIC MCU OTP 16KX16 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/L

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Number Of I /o: 52
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFPAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658IL; Q1162292

16.2.2
The receiver block diagram is shown in Figure 16-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter, operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at F
cally be used in RS-232 systems.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
FIGURE 16-4: USART RECEIVE BLOCK DIAGRAM
 2000 Microchip Technology Inc.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
USART ASYNCHRONOUS RECEIVER
RC7/RX/DT
Note:
I/O pins have diode protection to V
Baud Rate Generator
x64 Baud Rate CLK
SPBRG
Pin Buffer
and Control
OSC
SPEN
. This mode would typi-
Advanced Information
DD
Data
Recovery
and V
Interrupt
SS
CREN
.
÷ 64
÷ 16
or
16.2.3
This mode would typically be used in RS-485 systems.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
RCIF
RCIE
RX9
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is required,
set the BRGH bit.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCIF bit will be set when reception is com-
plete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
Read RCREG to determine if the device is being
addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
STOP
MSb
SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
RX9D
(8)
OERR
7
RSR Register
RCREG Register
• • •
8
PIC18CXX8
Data Bus
1
FERR
0
START
LSb
DS30475A-page 175
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