PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet - Page 257
![IC PIC MCU OTP 16KX16 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC18C658-I/L
Manufacturer Part Number
PIC18C658-I/L
Description
IC PIC MCU OTP 16KX16 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Number Of I /o
52
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Controller Family/series
PIC18
No. Of I/o's
52
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFPAC174007 - MODULE SKT PROMATEII 68PLCC
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C658IL
Q1162292
Q1162292
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-I/L
Manufacturer:
Microchip
Quantity:
385
Company:
Part Number:
PIC18C658-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18C658-I/L
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 257 of 366
- Download datasheet (7Mb)
22.3
Power-down mode is entered by executing a SLEEP
instruction.
Upon entering into Power-down mode, the following
actions are performed:
1.
2.
3.
4.
5.
To achieve lowest current consumption, follow these
steps before switching to Power-down mode:
1.
2.
3.
4.
5.
The MCLR pin must be at a logic high level (V
22.3.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
2000 Microchip Technology Inc.
Watchdog Timer is cleared and kept running.
PD bit in RCON register is cleared.
TO bit in RCON register is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before the
SLEEP instruction was executed.
Place all I/O pins at either V
ensure no external circuitry is drawing current
from I/O pin.
Power-down A/D and external clocks.
Pull all hi-impedance inputs to high or low
externally.
Place T0CKI at V
Current
pull-ups should be taken into account and dis-
abled if necessary.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
Power-down Mode (SLEEP)
WAKE-UP FROM SLEEP
consumption
SS
or V
DD
by
.
PORTB
DD
or V
Advanced Information
SS
on-chip
IHMC
and
).
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Activity on CAN bus receive line.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
PSP read or write.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
MSSP (START/STOP) bit detect interrupt.
MSSP transmit or receive in Slave mode
(SPI/I
USART RX or TX (Synchronous Slave mode).
A/D conversion (when A/D clock source is RC).
2
C).
PIC18CXX8
DS30475A-page 257
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