PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet
PIC18C658-I/L
Specifications of PIC18C658-I/L
Q1162292
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PIC18C658-I/L Summary of contents
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... Off-Chip Device # Single Maximum EPROM Word Addressing (bytes) Instructions (bytes) PIC18C658 32 K 16384 PIC18C858 32 K 16384 • MIPS operation MHz clock input - 4 MHz - 10 MHz osc./clock input with PLL active • 16-bit wide instructions, 8-bit wide data path • Priority levels for interrupts • ...
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... Pin Diagrams 64-Pin TQFP RE1/WR 2 RE0/RD 3 RG0/CANTX1 4 RG1/CANTX2 5 RG2/CANRX 6 RG3 7 MCLR RG4 RF7 12 RF6/AN11 13 RF5/AN10/CV REF 14 RF4/AN9 15 RF3/AN8 16 RF2/AN7/C1OUT DS30475A-page 2 PIC18C658 Advanced Information 48 RB0/INT0 47 RB1/INT1 46 RB2/INT2 45 RB3/INT3 44 RB4 43 RB5 42 RB6 OSC2/CLKO/RA6 39 OSC1/CLKI RB7 36 RC5/SDO 35 RC4/SDI/SDA 34 RC3/SCK/SCL 33 RC2/CCP1 2000 Microchip Technology Inc. ...
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... PLCC RE1/WR 11 RE0/RD 12 RG0/CANTX1 13 RG1/CANTX2 14 RG2/CANRX 15 RG3 16 MCLR RG4 RF7 22 RF6/AN11 23 RF5/AN10/CV REF RF4/AN9 24 RF3/AN8 25 26 RF2/AN7/C1OUT 2000 Microchip Technology Inc. PIC18C658 Advanced Information PIC18CXX8 60 RB0/INT0 59 RB1/INT1 58 RB2/INT2 57 RB3/INT3 56 RB4 55 RB5 54 RB6 OSC2/CLKO/RA6 50 OSC1/CLKI RB7 47 RC5/SDO 46 RC4/SDI/SDA 45 RC3/SCK/SCL 44 RC2/CCP1 DS30475A-page 3 ...
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... MCLR/V PP RG4 RF7 14 RF6/AN11 RF5/AN10/CV 15 REF RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 19 RH7/AN15 20 RH6/AN14 DS30475A-page PIC18C858 Advanced Information 60 RJ2 59 RJ3 58 RB0/INT0 57 RB1/INT1 56 RB2/INT2 55 RB3/INT3 54 RB4 53 RB5 52 RB6 OSC2/CLKO/RA6 OSC1/CLKI RB7 47 46 RC5/SDO RC4/SDI/SDA 45 RC3/SCK/SCL 44 RC2/CCP1 43 RK3 42 RK2 2000 Microchip Technology Inc. ...
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... RH2 12 13 RH3 RE1/WR 14 RE0/RD 15 RG0/CANTX1 16 RG1/CANTX2 17 RG2/CANRX 18 RG3 19 MCLR RG4 RF7 25 RF6/AN11 26 RF5/AN10/CV REF 27 RF4/AN9 28 RF3/AN8 29 RF2/AN7/C1OUT 30 RH7/AN15 31 RH6/AN14 2000 Microchip Technology Inc PIC18C858 Advanced Information PIC18CXX8 75 RJ2 74 RJ3 73 RB0/INT0 72 RB1/INT1 71 RB2/INT2 70 69 RB3/INT3 68 RB4 67 RB5 66 RB6 OSC2/CLKO/RA6 62 OSC1/CLKI 61 ...
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... Device Differences..................................................................................................................................................... 349 Appendix C: Device Migrations ...................................................................................................................................................... 350 Appendix D: Migrating from other PICmicro Devices ..................................................................................................................... 350 Appendix E: Development Tool Version Requirements ................................................................................................................. 351 Index .................................................................................................................................................................................................. 353 On-Line Support................................................................................................................................................................................. 361 Reader Response .............................................................................................................................................................................. 362 PIC18CXX8 Product Identification System ........................................................................................................................................ 363 DS30475A-page 6 Advanced Information 2000 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2000 Microchip Technology Inc. Advanced Information PIC18CXX8 DS30475A-page 7 ...
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... PIC18CXX8 NOTES: DS30475A-page 8 Advanced Information 2000 Microchip Technology Inc. ...
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... This document contains device specific information for the following three devices: 1. PIC18C658 2. PIC18C858 The PIC18C658 is available in 64-pin TQFP and 68-pin PLCC packages. The PIC18C858 is available in 80-pin TQFP and 84-pin PLCC packages. An overview of features is shown in Table 1-1. TABLE 1-1: DEVICE FEATURES Features ...
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... PIC18CXX8 FIGURE 1-1: PIC18C658 BLOCK DIAGRAM Table Pointer<21> inc/dec logic 20 PCLATU PCU Program Counter Address Latch Program Memory 31 Level Stack (32 Kbytes) Data Latch TABLELATCH 8 16 ROMLATCH Instruction Decode & Control Power-up OSC2/CLKO Timer OSC1/CLKI Oscillator Timing Generation Start-up Timer Power-on Reset ...
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... Watchdog Timer Precision Brown-out Bandgap Reset Reference MCLR PORTK RK0 RK1 RK2 RK3 BOR Timer0 Timer1 LVD Comparator CCP1 2000 Microchip Technology Inc. Data Bus<8> Data Latch 8 8 Data RAM ( 1 Address Latch PCLATH 12 Address<12> PCH PCL BSR Bank0, F FSR0 FSR1 ...
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... PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18C658 TQFP PLCC MCLR MCLR — 1, 18, 35, 52 OSC1/CLKI 39 50 OSC1 CLKI OSC2/CLKO/RA6 40 51 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS30475A-page 12 ...
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... TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RA0/AN0 24 34 RA0 AN0 RA1/AN1 23 33 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 39 RA4 T0CKI RA5/AN4/SS/LVDIN 27 38 RA5 AN4 SS LVDIN RA6 ...
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... PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RB0/INT0 48 60 RB0 INT0 RB1/INT1 47 59 RB1 INT1 RB2/INT2 46 58 RB2 INT2 RB3/INT3 45 57 RB3 INT3 RB4 44 56 RB5 43 55 RB6 42 54 RB7 37 48 Legend: TTL = TTL compatible input ...
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... TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RC0/T1OSO/T13CKI 30 41 RC0 T1OSO T13CKI RC1/T1OSI 29 40 RC1 T1OSI RC2/CCP1 33 44 RC2 CCP1 RC3/SCK/SCL 34 45 RC3 SCK SCL RC4/SDI/SDA 35 46 RC4 SDI SDA RC5/SDO 36 47 RC5 SDO RC6/TX/CK ...
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... PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RD0/PSP0 58 3 RD0 PSP0 RD1/PSP1 55 67 RD1 PSP1 RD2/PSP2 54 66 RD2 PSP2 RD3/PSP3 53 65 RD3 PSP3 RD4/PSP4 52 64 RD4 PSP4 RD5/PSP5 51 63 RD5 PSP5 RD6/PSP6 50 62 RD6 ...
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... TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RE0/ RE0 RD RE1/ RE1 WR RE2/ RE2 CS RE3 63 8 RE4 62 7 RE5 61 6 RE6 60 5 RE7/CCP2 59 4 RE7 CCP2 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RF0/AN5 18 28 RF0 AN5 RF1/AN6/C2OUT 17 27 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 26 RF2 AN7 C1OUT RF3/AN8 15 25 RF1 AN8 RF4/AN9 14 24 RF1 AN9 RF5/AN10/ REF RF1 AN10 CV REF ...
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... TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RG0/CANTX1 3 12 RG0 CANTX1 RG1/CANTX2 4 13 RG1 CANTX2 RG2/CANRX 5 14 RG2 CANRX RG3 6 15 RG4 8 17 RH0 — — RH1 — — RH2 — — RH3 — — ...
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... PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC RJ0 — — RJ0 — — RJ0 RJ1 — — RJ1 — — RJ1 RJ2 — — RJ2 — — RJ2 RJ3 — — RJ3 — — ...
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... Figure 2-4. The PIC18CXX8 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. 2000 Microchip Technology Inc. FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OSC CONFIGURATION) (1) ...
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... TBD ± 0.3% ± 0.5% ± 0.5% ± 0.5% ± 0.5% Cap. Range 47- 15-33 pF 15-33 pF TBD 15 pF 15-33 pF TBD ± 20 PPM ± 20 PPM ± 50 PPM ± 50 PPM ± 30 PPM ± 30 PPM Advanced Information 2000 Microchip Technology Inc. ...
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... The RCIO oscillator mode functions like the RC mode, except that the OSC2 pin becomes an additional gen- eral purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). 2000 Microchip Technology Inc. 2.4 External Clock Input The EC and ECIO oscillator modes require an external clock source to be connected to the OSC1 pin ...
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... A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out referred FOSC2:FOSC0 = ‘110’ Phase Loop Filter OUT Divide by 4 Advanced Information . PLL VCO SYSCLK 2000 Microchip Technology Inc. ...
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... OSCSEN is clear or T1OSCEN is clear: bit is forced clear Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. 2.6.1 SYSTEM CLOCK SWITCH BIT The system clock source switching is performed under software control. The system clock switch bit, SCS (OSCCON register), controls the clock switching. When the SCS bit is ’ ...
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... XT, LP), the transition will take place after an oscillator start-up time (T diagram indicating the transition from the Timer1 oscil- lator to the main oscillator for HS, XT and LP modes is shown in Figure 2- Tscs OST T SCS T OSC Advanced Information ) has occurred. A timing OST 2000 Microchip Technology Inc. ...
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... Program Counter PC Note 1: RC oscillator mode assumed. 2000 Microchip Technology Inc. If the main oscillator is configured in the RC, RCIO ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram indicat- ...
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... PLL ample time to lock to the incoming clock frequency. OSC1 Pin At logic low Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low Feedback inverter disabled, at quiescent voltage level Advanced Information (parameter PWRT (parameter PLL OSC2 Pin 2000 Microchip Technology Inc. ...
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... Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2000 Microchip Technology Inc. state on Power-on Reset, MCLR, WDT Reset, Brown-out Reset, MCLR Reset during SLEEP and by the RESET instruction. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation ...
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... Brown-out Reset and the Power-up Timer will be initialized. Once V Timer will execute the additional time delay. Advanced Information to rise bit, BOREN, can disable (if falls below parameter D005 for DD falls DD rises DD drops below BV while DD DD rises above BV , the Power- 2000 Microchip Technology Inc. ...
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... Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2000 Microchip Technology Inc. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30475A-page 32 T PWRT T OST T PWRT T PWRT Advanced Information ) DD ): CASE OST ): CASE OST 2000 Microchip Technology Inc. ...
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... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET T = 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL 2000 Microchip Technology Inc DEADTIME T PWRT T OST T PWRT T OST ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu uuuu (1) uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A 2000 Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. 2000 Microchip Technology Inc. MCLR Reset Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. 2000 Microchip Technology Inc. MCLR Reset Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ’0’. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. 2000 Microchip Technology Inc. MCLR Reset Power-on Reset, WDT Reset ...
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... Microchip Technology Inc. ...
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... The reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Figure 4-1 shows the diagram for program memory map and stack for the PIC18C658 and PIC18C858. 4.1.1 INTERNAL PROGRAM MEMORY OPERATION All devices have 32 Kbytes of internal EPROM program memory ...
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... The STKUNF bit will remain set until cleared in software or a POR occurs. Note: Returning a value of zero to the underflow has the effect of vectoring the program to the RESET vector, where the stack conditions can be verified and appro- priate actions can be taken. Advanced Information 2000 Microchip Technology Inc. ...
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... Value at POR FIGURE 4-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS TOSU TOSH 0x00 0x1A Note 1: No RAM associated with this address; always maintained ‘0’s. 2000 Microchip Technology Inc. U-0 R/W-0 R/W-0 — SP4 SP3 W = Writable bit U = Unimplemented bit, read as ‘0’ ...
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... EXAMPLE 4-1: CALL SUB1, FAST • • • SUB1 • • RETURN FAST Advanced Information FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2000 Microchip Technology Inc. ...
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... OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-2) 2000 Microchip Technology Inc. The contents of PCLATH and PCLATU will be trans- ferred to the program counter by an operation that writes PCL. Similarly, the upper two bytes of the pro- gram counter will be transferred to PCLATH and PCLATU by an operation that reads PCL ...
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... Execute 2 Fetch 3 Execute 3 Fetch 4 Opcode Memory 55h 0Eh 03h EFh 00h F0h 23h C1h 56h F4h Advanced Information Flush Fetch SUB_1 Execute SUB_1 Address 000007h 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h 000011h 000012h 2000 Microchip Technology Inc. ...
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... TSTFSZ 1100 0001 0010 0011 MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2000 Microchip Technology Inc. 4.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). A lookup table can be formed with an ADDWF instruction and a group of RETLW 0xnn instructions. ...
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... The SFR’s are typically distributed among the peripher- als whose functions they control. The unused SFR locations will be unimplemented and read as '0's. See Table 4-2 for addresses for the SFR’s. Advanced Information 2000 Microchip Technology Inc. ...
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... FIGURE 4-4: DATA MEMORY MAP FOR PIC18C658/858 BSR<3:0> 00h = 0000b Bank 0 FFh 00h = 0001b Bank 1 FFh 00h = 0010b Bank 2 FFh 00h = 0011b Bank 3 FFh = 0100b Bank 4 00h = 0101b Bank 5 FFh = 0110b Bank 1110b Bank 14 00h = 1111b Bank 15 FFh 2000 Microchip Technology Inc. ...
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... F91h LATJ (5) F90h LATH F8Fh LATG F8Eh LATF F8Dh LATE F8Ch LATD F8Bh LATC F8Ah LATB F89h LATA (5) F88h PORTJ (5) F87h PORTH F86h PORTG F85h PORTF F84h PORTE F83h PORTD F82h PORTC F81h PORTB F80h PORTA 2000 Microchip Technology Inc. ...
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... Contents of register is dependent on WIN2:WIN0 bits in CANCON register. 4: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip Header file requirement. 5: Available on PIC18C858 only. 2000 Microchip Technology Inc. Name Address Name F3Fh — ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 52 Bit 4 Bit 3 Bit 2 — ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 — ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 54 Bit 4 Bit 3 Bit 2 DC1B0 ...
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... Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Read PORTG Data Latch, Write PORTG Data Latch ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 56 Bit 4 Bit 3 Bit 2 RXB0D74 ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 TXB0D74 ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. DS30475A-page 58 Bit 4 Bit 3 Bit 2 TXB2D74 ...
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... Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read ‘0’. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. 4: These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 EID4 ...
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... Section 4.12 provides a description of indirect address- ing, which allows linear addressing of the entire RAM space. (3) from opcode 0 (3) 00h 01h 000h 100h (1) 0FFh 1FFh Bank 0 Bank 1 Advanced Information 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15 2000 Microchip Technology Inc. ...
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... FSR register being the address of the data. 2000 Microchip Technology Inc instruction writes a value to INDF0, the value will be written to the address indicated by FSR0H:FSR0L. A read from INDF1 reads the data from the address indicated by FSR1H:FSR1L ...
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... PIC18CXX8 FIGURE 4-6: INDIRECT ADDRESSING 11 FSRnH location select Note 1: For register file map detail, see Table 4-2. DS30475A-page 62 Indirect Addressing FSR register FSRnL 0000h Data (1) Memory 0FFFh Advanced Information 2000 Microchip Technology Inc. ...
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... Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). ...
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... Power-on Resets may be detected. U-0 R/W-1 R/W-1 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information necessarily predictable if the R/W-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2000 Microchip Technology Inc. ...
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... Instruction: TBLWT* Note 1: Table Pointer points to a byte in program memory. 2000 Microchip Technology Inc. Table Read operations retrieve data from program memory and place it into the data memory space. Figure 5-1 shows the operation of a Table Read with program and data memory. ...
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... POR or MCLR Reset. U-0 R/W-1 R/W-1 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information voltage is applied to the PP R/W-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2000 Microchip Technology Inc. ...
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... TBLWT*- TBLRD+* TBLPTR is incremented before the read/write TBLWT+* 2000 Microchip Technology Inc. address Mbytes of program memory space. The 22nd bit allows read only access to the Device ID, the User ID and the Configuration bits. The table pointer TBLPTR is used by the TBLRD and TBLWT instructions ...
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... MOVWF TABLAT DataLow TBLWT*+ MOVLW DataHigh LSB MOVWF TABLAT DataLow TBLWT* Advanced Information ; Load low data ; byte to TABLAT ; Write it to LSB ; of Holding register ; Load high data ; byte to TABLAT ; Write it to MSB ; of Holding ; register and ; begin long ; write 2000 Microchip Technology Inc. ...
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... RESET or an interrupt. Having only one interrupt source enabled to terminate the long write, ensures that no unintended interrupts will prematurely terminate the long write. 2000 Microchip Technology Inc. 5.2.2.2 Sequence of Events The sequence of events for programming an internal program memory location should be: 1 ...
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... Terminates long write, executes next instruction. Interrupt flag not cleared Terminates long write, branches to low priority interrupt vector. Interrupt flag can be cleared by ISR Terminates long write, branches to high priority interrupt vector. Interrupt flag can be cleared by ISR. Advanced Information Action 2000 Microchip Technology Inc. ...
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... Without hardware multiply Hardware multiply signed Without hardware multiply Hardware multiply 2000 Microchip Technology Inc. Making the multiplier execute in a single cycle gives the following advantages: • Higher computational throughput • Reduces code size requirements for multiply algo- rithms ...
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... ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • (ARG1L • ARG2L UNSIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; 2000 Microchip Technology Inc. ...
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... ARG2L • (ARG1L • ARG2H • (ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 2 (-1 • ARG1H<7> • ARG2H:ARG2L • 2 2000 Microchip Technology Inc. EXAMPLE 6-4: MOVFF ARG1L, WREG MULWF ARG2L MOVFF PRODH, RES1 MOVFF PRODL, RES0 ; MOVFF ...
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... PIC18CXX8 NOTES: DS30475A-page 74 Advanced Information 2000 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their cor- responding enable bits. 2000 Microchip Technology Inc. When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- patible ...
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... GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Advanced Information Wake- SLEEP mode Interrupt to CPU Vector to location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL 2000 Microchip Technology Inc. ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2000 Microchip Technology Inc. 7.1.1 INTCON REGISTERS The INTCON Registers are readable and writable registers, which contain various enable, priority, and flag bits ...
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... DS30475A-page 78 R/W-1 R/W-1 R/W-1 INTEDG1 INTEDG2 INTEDG3 TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information R/W-1 R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2000 Microchip Technology Inc. ...
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... Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2000 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ...
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... U-0 R/W-1 R/W-1 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information for the peripheral interrupts R/W-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2000 Microchip Technology Inc. ...
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... TMR2 to PR2 match occurred (must be cleared in software TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow 2000 Microchip Technology Inc. R-0 R-0 R/W-0 RCIF TXIF SSPIF U-0 ...
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... Capture Mode TMR1 register capture occurred (must be cleared in software TMR1 register capture occurred Compare Mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM Mode Unused in this mode DS30475A-page 82 Advanced Information 2000 Microchip Technology Inc. ...
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... RXB0IF: Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information ...
Page 84
... SSPIE U-0 U-0 R/W-0 — — BCLIE R/W-1 R/W-1 R/W-1 ERRIE TXB2IE TXB1IE Advanced Information R/W-0 R/W-0 R/W-0 CCP1IE TMR2IE TMR1IE bit 0 R/W-0 R/W-0 R/W-0 LVDIE TMR3IE CCP2IE bit 0 R/W-1 R/W-1 R/W-1 TXB0IE RXB1IE RXB0IE bit 0 2000 Microchip Technology Inc. ...
Page 85
... RXB0IE: Receive Buffer 0 Interrupt Enable bit 1 = Enables the Receive Buffer 0 Interrupt 0 = Disables the Receive Buffer 0 Interrupt Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information ...
Page 86
... SSPIP U-0 U-0 R/W-1 — — BCLIP R/W-1 R/W-1 R/W-1 ERRIP TXB2IP TXB1IP Advanced Information R/W-1 R/W-1 R/W-1 CCP1IP TMR2IP TMR1IP bit 0 R/W-1 R/W-1 R/W-1 LVDIP TMR3IP CCP2IP bit 0 R/W-1 R/W-1 R/W-1 TXB0IP RXB1IP RXB0IP bit 0 2000 Microchip Technology Inc. ...
Page 87
... RXB0IP: Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information PIC18CXX8 x = Bit is unknown ...
Page 88
... Example 7-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in Low Access bank ; STATUS_TEMP located anywhere ; BSR located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Advanced Information 2000 Microchip Technology Inc. ...
Page 89
... The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. 2000 Microchip Technology Inc. EXAMPLE 8-1: CLRF PORTA ...
Page 90
... P (1) I/O Pin ECRA6 or RCRA6 Enable TTL Input Buffer and REF +. REF Value on Value on all Bit 0 POR, other BOR RESETS RA0 -x0x 0000 -uuu uuuu -xxx xxxx -uuu uuuu -111 1111 -111 1111 PCFG0 --00 0000 --uu uuuu 2000 Microchip Technology Inc. ...
Page 91
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). 2000 Microchip Technology Inc. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is per- formed by clearing bit RBPU (INTCON2 register). The weak pull-up is automatically turned off when the port pin is configured as an output ...
Page 92
... Value on Value on Bit 0 POR, all other BOR RESETS RB0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u RBIP 1111 1111 1111 1111 INT1IF 1100 0000 1100 0000 2000 Microchip Technology Inc. ...
Page 93
... RC5 RC6 RC7 Note: I/O pins have diode protection to V 2000 Microchip Technology Inc. put, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the correspond- ing peripheral section for the correct TRIS bit settings. ...
Page 94
... Addressable USART Synchronous Data. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RC4 RC3 RC2 RC1 RC0 Advanced Information 2 C. Value on Value on all POR, other BOR RESETS xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 2000 Microchip Technology Inc. ...
Page 95
... MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD3:RD0 as inputs ; RD5:RD4 as outputs ; RD7:RD6 as inputs 2000 Microchip Technology Inc. FIGURE 8-7: PORTD BLOCK DIAGRAM IN I/O PORT MODE Data Bus D WR LATD PORTD Data Latch ...
Page 96
... Bit 2 Bit 1 RD4 RD3 RD2 RD1 — — — Advanced Information Function Value on Value on all POR, other Bit 0 BOR RESETS RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 — 0000 ---- 0000 ---- 2000 Microchip Technology Inc. ...
Page 97
... TRIS Latch RD TRISE Peripheral Enable RD PORTE Peripheral Data In Pin RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 Note 1: I/O pins have diode protection to V 2000 Microchip Technology Inc. EXAMPLE 8-5: CLRF PORTE CLRF LATE MOVLW 0x03 MOVWF TRISE LATE Q Q Latch ...
Page 98
... Input/output port pin or Capture 2 input/Compare 2 output. Bit 3 Bit 2 Bit 1 — — — Advanced Information Value on: Value on all Bit 0 POR, other BOR RESETS 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — 0000 ---- 0000 ---- 2000 Microchip Technology Inc. ...
Page 99
... PORTF Latch Data TRISF CK Q TRIS Latch RD TRISF RD PORTF To A/D Converter Note: I/O pins have diode protection to V 2000 Microchip Technology Inc. EXAMPLE 8-6: CLRF PORTF CLRF LATF MOVLW 0x07 MOVWF CMCON MOVLW 0x0F MOVWF ADCON1 MOVLW 0xCF MOVWF TRISF ...
Page 100
... Data Latch D Q Schmitt Trigger CK Input Buffer TRIS Latch RD TRISF and Value on: Value on all Bit 0 POR, other RESETS BOR 1111 1111 1111 1111 xxxx xxxx uuuu uuuu 0000 0000 uuuu uuuu --00 0000 CM0 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 101
... FIGURE 8-12: RG0/CANTX0 PIN BLOCK DIAGRAM TXD RD LATG Data Bus D WR PORTG or WR LATG CK Latch Data D WR TRISG CK TRIS Latch RD TRISG RD PORTG Note: I/O pins have diode protection to V 2000 Microchip Technology Inc. EXAMPLE 8-7: CLRF PORTG CLRF LATG MOVLW 0x04 MOVWF TRISG OPMODE2:OPMODE0 = 000 Q ...
Page 102
... WR PORTG WR TRISG RD PORTG Note: I/O pins have diode protection to V and Advanced Information OPMODE2:OPMODE0=000 TX1EN ENDRHI I/O Pin Schmitt Trigger DIAGRAM RD LATG D Q I/O Pin CK Latch Data D Q Schmitt Trigger CK Input Buffer TRIS Latch RD TRISG and 2000 Microchip Technology Inc. ...
Page 103
... Read PORTG Data Latch/Write PORTG Data Latch CIOCON TX1SRC TX1EN ENDRHI CANCAP Legend unknown unchanged 2000 Microchip Technology Inc. Function Input/output port pin or CAN bus transmit output. Input/output port pin or CAN bus complimentary transmit output or CAN bus bit time clock. ...
Page 104
... Alternate method ; to clear output ; data latches ; ; ; Value used to ; initialize data ; direction ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs DIAGRAM RD LATH Data Latch N I/O Pin Analog TRIS Latch Input Mode ST RD TRISH Input Buffer and 2000 Microchip Technology Inc. ...
Page 105
... Read PORTH Data Latch/Write PORTH Data Latch ADCON1 — — VCFG1 VCFG0 PCFG3 Legend unknown unchanged unimplemented 2000 Microchip Technology Inc. Function Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin or analog input channel 12. ...
Page 106
... MOVWF TRISJ Schmitt Trigger and Advanced Information INITIALIZING PORTJ ; Initialize PORTJ by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as outputs ; RJ7:RJ6 as inputs I/O Pin 2000 Microchip Technology Inc. ...
Page 107
... PORTJ Data Direction Control Register PORTJ Read PORTJ pin/Write PORTJ Data Latch LATJ Read PORTJ Data Latch/Write PORTJ Data Latch Legend unknown unchanged 2000 Microchip Technology Inc. Function Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. ...
Page 108
... Input/output port pin. Bit 3 Bit 2 Bit 1 Bit 0 Advanced Information RD LATK Q I/O Pin Q Schmitt Trigger Input Buffer RD TRISK and Value on: Value on all POR, BOR other RESETS 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
Page 109
... Register) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). In this mode, the input buffers are TTL. 2000 Microchip Technology Inc. FIGURE 9-1: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) ...
Page 110
... Value at POR DS30475A-page 110 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information U-0 U-0 U-0 — — — bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 111
... GIEH GIEL PIR1 PSPIF ADIF RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP Legend unknown unchanged unimplemented, read as ’0’. Shaded cells are not used by the Parallel Slave Port. 2000 Microchip Technology Inc Bit 4 Bit 3 Bit 2 Bit 1 RE4 RE3 ...
Page 112
... PIC18CXX8 NOTES: DS30475A-page 112 Advanced Information 2000 Microchip Technology Inc. ...
Page 113
... Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. Register 10-1 shows the Timer0 Control register (T0CON). Figure 10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 10-1 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 114
... SS 0 Sync with Internal TMR0L Clocks delay) CY PSA 8 and Advanced Information Data Bus 8 TMR0L Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 TMR0H 8 Data Bus<7:0> 2000 Microchip Technology Inc. ...
Page 115
... Also, there is a delay in the actual OSC incrementing of Timer0 after synchronization. 2000 Microchip Technology Inc. 10.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable ...
Page 116
... TMR0IF INT0IF T0CS T0SE PSA T0PS2 T0PS1 (1) Advanced Information Value on Value on all other Bit 0 POR, BOR RESETS xxxx xxxx uuuu uuuu 0000 0000 0000 0000 RBIF 0000 000x 0000 000u T0PS0 1111 1111 1111 1111 --11 1111 --11 1111 2000 Microchip Technology Inc. ...
Page 117
... Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. Register 11-1 shows the Timer1 control register. This register controls the operating mode of the Timer1 module as well as contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON register) ...
Page 118
... F /4 OSC (1) Internal 0 Clock 2 T1CKPS1:T1CKPS0 TMR1CS 8 Special Event Trigger TMR1L TMR1ON T1SYNC On/Off 1 Prescaler Fosc/4 Internal 0 (1) Clock TMR1CS T1CKPS1:T1CKPS0 Advanced Information Synchronized Clock Input Synchronize det SLEEP Input Synchronized 0 Clock Input 1 Synchronize det 2 SLEEP Input 2000 Microchip Technology Inc. ...
Page 119
... TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR regis- ters). This interrupt can be enabled/disabled by set- ting/clearing TMR1 interrupt enable bit TMR1IE (PIE registers). 2000 Microchip Technology Inc. 11.4 Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in Compare mode ...
Page 120
... Bit 0 POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0-00 0000 u-uu uuuu 2000 Microchip Technology Inc. ...
Page 121
... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. 12.1 Timer2 Operation Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (F of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON Register) ...
Page 122
... POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0000 0000 0000 0000 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 2000 Microchip Technology Inc. ...
Page 123
... Enables Timer3 0 = Stops Timer3 Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. Figure 13 simplified block diagram of the Timer3 module. Register 13-1 shows the Timer3 Control Register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 124
... Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Trigger T3CCPx CLR TMR3L TMR3ON On/Off T3SYNC 1 Prescaler OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Advanced Information Synchronized Clock Input Synchronize det 2 SLEEP Input Synchronized 0 Clock Input 1 Synchronize det 2 SLEEP Input 2000 Microchip Technology Inc. ...
Page 125
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. 2000 Microchip Technology Inc. 13.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3 ...
Page 126
... PIC18CXX8 NOTES: DS30475A-page 126 Advanced Information 2000 Microchip Technology Inc. ...
Page 127
... Trigger special event (CCPIF bit is set, reset TMR1 or TMR3) 11xx = PWM mode Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. Section 17.0 for CAN operation.) Therefore, operation of a CCP module in the following sections is described with respect to CCP1. Table 14-2 shows the interaction of the CCP modules. ...
Page 128
... The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Syn- chronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. Interaction Advanced Information 2000 Microchip Technology Inc. ...
Page 129
... CCP2M3:CCP2M0 Q’s Note: I/O pins have diode protection to V 2000 Microchip Technology Inc. 14.3.5 CAN MESSAGE RECEIVED The CAN capture event occurs when a message is received in either receive buffer. The CAN module pro- vides a rising edge to the CCP module to cause a cap- ture event ...
Page 130
... Set Flag bit CCP1IF Output Logic match CCP1M3:CCP1M0 T3CCP2 Mode Select TMR1H Set Flag bit CCP2IF T3CCP1 T3CCP2 Output Logic Match CCP2M3:CCP2M0 Mode Select and Advanced Information CCPR1H CCPR1L Comparator 1 0 TMR1L TMR3H TMR3L 0 1 Comparator CCPR2H CCPR2L 2000 Microchip Technology Inc. ...
Page 131
... Holding register for the Most Significant Byte of the 16-bit TMR3 register T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. 2000 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 INT0IE ...
Page 132
... If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. Advanced Information [(PR2 • 4 • T • OSC (TMR2 prescale value) (CCPR1L:CCP1CON<5:4>) • T • (TMR2 prescale value) OSC F OSC log --------------- F PWM = -----------------------------bits log 2000 Microchip Technology Inc. ...
Page 133
... CMIF — PIE2 — CMIE — IPR2 — CMIP — Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. 2000 Microchip Technology Inc. 2.44 kHz 9.76 kHz 39.06 kHz 156.3 kHz 0xFF 0xFF 0xFF 10 10 ...
Page 134
... PIC18CXX8 NOTES: DS30475A-page 134 Advanced Information 2000 Microchip Technology Inc. ...
Page 135
... Serial Peripheral Interface (SPI) 2 • Inter-Integrated Circuit ( Full Master mode - Slave mode (with general address call) 2 The I C interface supports the following modes in hardware: • Master mode • Multi-master mode • Slave mode 2000 Microchip Technology Inc. Advanced Information PIC18CXX8 DS30475A-page 135 ...
Page 136
... Register 15-1 shows the MSSP Status Register (SSPSTAT), Register 15-2 shows the MSSP Control Register 1 (SSPCON1), and Register 15-3 shows the MSSP Control Register 2 (SSPCON2). R-0 R-0 R-0 D mode only mode only) Advanced Information R-0 R-0 R-0 R bit 0 2000 Microchip Technology Inc. ...
Page 137
... Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc mode only modes Writable bit U = Unimplemented bit, read as ‘ ...
Page 138
... Holds clock low (clock stretch). (Used to ensure data setup time Master mode Unused in this mode DS30475A-page 138 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 Advanced Information R/W-0 R/W-0 R/W-0 SSPM2 SSPM1 SSPM0 bit conditions were not valid for a 2000 Microchip Technology Inc. ...
Page 139
... I C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. /4 OSC /16 OSC /64 OSC / (4 * (SSPADD+1) ) OSC W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 140
... C Master mode only Master mode only Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information R/W-0 R/W-0 R/W-0 PEN RSEN SEN bit module is not in the IDLE x = Bit is unknown 2000 Microchip Technology Inc. ...
Page 141
... SCK) • Clock rate (Master mode only) • Slave Select mode (Slave mode only) Figure 15-1 shows the block diagram of the MSSP module, when in SPI mode. 2000 Microchip Technology Inc. FIGURE 15-1: MSSP BLOCK DIAGRAM (SPI MODE) Read SDI SDO ...
Page 142
... SCK (Slave mode) must have TRISC<3> bit set • SS must have TRISC<4> bit set Any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (TRIS) register to the opposite value. Advanced Information 2000 Microchip Technology Inc. ...
Page 143
... Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF 2000 Microchip Technology Inc. shown in Figure 15-2, Figure 15-4, and Figure 15-5, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • ( ...
Page 144
... SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict. bit6 bit7 bit7 Advanced Information . DD bit0 bit0 Next Q4 Cycle after Q2 ↓ 2000 Microchip Technology Inc. ...
Page 145
... CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit7 SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF 2000 Microchip Technology Inc. bit6 bit5 bit4 bit2 bit3 bit6 bit2 bit5 bit4 bit3 Advanced Information PIC18CXX8 bit1 bit0 bit0 Next Q4 Cycle after Q2 ↓ ...
Page 146
... RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 BF 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 147
... Serial Receive/Transmit Buffer (SSPBUF) • MSSP Shift Register (SSPSR) - Not directly accessible • MSSP Address Register (SSPADD) 2000 Microchip Technology Inc. The SSPCON1 register allows control of the I ation. The SSPM3:SSPM0 mode selection bits (SSPCON1 register) allow one of the following I ...
Page 148
... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive repeated START condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Advanced Information 2000 Microchip Technology Inc. ...
Page 149
... Data in Sampled SSPIF BF CKP 2000 Microchip Technology Inc. ter. Then pin RC3/SCK/SCL should be enabled by set- ting bit CKP (SSPCON1 register). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock ...
Page 150
... Acknowledge (Figure 15-9). Address is compared to General Call Address after ACK, set interrupt Receiving data ACK Cleared in software SSPBUF is read Advanced Information ACK ’0’ ’1’ 2000 Microchip Technology Inc. ...
Page 151
... SDA SDA In SCL SCL In Bus Collision Note: I/O pins have diode protection to V 2000 Microchip Technology Inc. 2 15.4 MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. Once Master mode is enabled, the user has the following six options: 1 ...
Page 152
... The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. k) The user generates a STOP condition by setting the STOP Enable bit PEN (SSPCON2 register). l) Interrupt is generated once the STOP condition is complete. Advanced Information 2000 Microchip Technology Inc. ...
Page 153
... SCL low (clock arbitration) SCL BRG 03h value BRG reload 2000 Microchip Technology Inc. remented twice per instruction cycle (T and Q4 clocks reloaded automatically. If Clock Arbitration is taking place, for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 15-12). SSPM3:SSPM0 SSPADD< ...
Page 154
... SSPCON2 is disabled until the START condition is complete. Set S bit (SSPSTAT) SDA = 1, At completion of START bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit T T BRG BRG Write to SSPBUF occurs here 1st Bit T BRG T BRG S Advanced Information 2nd Bit 2000 Microchip Technology Inc. ...
Page 155
... SDA Falling edge of ninth clock End of Xmit SCL 2000 Microchip Technology Inc. Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is ...
Page 156
... WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). Advanced Information 2000 Microchip Technology Inc. ...
Page 157
... FIGURE 15-15 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) 2000 Microchip Technology Inc. Advanced Information PIC18CXX8 DS30475A-page 157 ...
Page 158
... PIC18CXX8 2 FIGURE 15-16 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS30475A-page 158 Advanced Information 2000 Microchip Technology Inc. ...
Page 159
... SSPIF Set SSPIF at the end of receive Note one baud rate generator period. BRG 2000 Microchip Technology Inc. 15.4.11 STOP CONDITION TIMING A STOP bit is asserted on the SDA pin at the end of a bit ACKEN receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2 register). At the end of a receive/transmit, the SCL line is held low after the fall- ing edge of the ninth clock ...
Page 160
... SDA sampled high. P bit (SSPSTAT) is set PEN bit (SSPCON2) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to set up STOP condition. Advanced Information BRG 2000 Microchip Technology Inc. ...
Page 161
... Release SCL, Slave device holds SCL low. to measure high time interval. SCL SDA T BRG 2000 Microchip Technology Inc. 15.4.13 SLEEP OPERATION While in SLEEP mode, the I addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled). ...
Page 162
... S and P bits are cleared. Sample SDA. While SCL is high SDA line pulled low by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master Advanced Information Set bus collision interrupt (BCLIF) 2000 Microchip Technology Inc. ...
Page 163
... BCLIF SDA = 0, SCL = 1. S SSPIF 2000 Microchip Technology Inc. The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD<6:0> and counts down the SCL pin is sampled low ...
Page 164
... Set S Set SSPIF BRG T BRG S SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SDA = 0, SCL = 1 Set SSPIF Advanced Information Interrupt cleared in software ’0’ ’0’ ’0’ Interrupts cleared in software 2000 Microchip Technology Inc. ...
Page 165
... BCLIF Set BCLIF, release SDA and SCL. RSEN S SSPIF 2000 Microchip Technology Inc. reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. ...
Page 166
... T T BRG BRG T BRG SCL goes low before SDA goes high, set BCLIF Advanced Information SDA sampled T BRG low after T , BRG set BCLIF ’0’ ’0’ T BRG ’0’ ’0’ 2000 Microchip Technology Inc. ...
Page 167
... TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit. Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) The SPEN (RCSTA register) and the TRISC< ...
Page 168
... Value at POR DS30475A-page 168 R/W-0 R/W-0 R/W-0 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 169
... RX9 SREN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used by the BRG. 2000 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the F OSC baud rate error in some cases ...
Page 170
... KBAUD ERROR - 185 9.60 0 131 92 19. 74.54 -2. 97.48 +1. 316.80 +5. 422.40 -15. 1267. 255 4.95 - 255 32.768 kHz SPBRG SPBRG value value % (decimal) (decimal) KBAUD ERROR - 0.30 +1.14 26 207 1.17 -2.48 6 103 2.73 +13. 8.20 -14. 8. 255 0.03 - 255 2000 Microchip Technology Inc. ...
Page 171
... 300 500 HIGH 62. 55.93 LOW 0.24 - 255 0.22 2000 Microchip Technology Inc. 33 MHz 25 MHz SPBRG value % % (decimal) ERROR KBAUD ERROR - - -0.07 214 2.40 -0.15 -0.54 53 9.53 -0.76 -0.54 26 19.53 +1.73 -4.09 6 78.13 +1.73 +7 ...
Page 172
... KBAUD ERROR - 185 2.40 0 131 46 9. 18.64 -2. 79.20 +3. 105.60 +10. 316.80 +5. 316. 255 1.24 - 255 32.768 kHz SPBRG SPBRG value value % (decimal) (decimal) KBAUD ERROR 207 0.29 -2. 1.02 -14. 2.05 -14. 2. 255 0.008 - 255 2000 Microchip Technology Inc. ...
Page 173
... Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator 2000 Microchip Technology Inc. Once the TXREG register transfers the data to the TSR register (occurs in one T standard empty and flag bit TXIF (PIR registers) is set. This inter- rupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers) ...
Page 174
... Word 2 Word 2 Transmit Shift Reg. Value on Value on Bit 0 POR, all other BOR RESETS RBIF 0000 000x 0000 000u RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 175
... RC7/RX/DT Pin Buffer and Control SPEN Note: I/O pins have diode protection to V 2000 Microchip Technology Inc. 16.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. Steps to follow when setting up an Asynchronous Reception with Address Detect Enable: 1 ...
Page 176
... BOR RESETS RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0010 0000 0010 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 177
... SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. 2000 Microchip Technology Inc. enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software ...
Page 178
... FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS30475A-page 178 Bit 1 Bit 2 Bit 7 Bit 0 Word 1 bit0 bit2 bit1 Advanced Information Bit 1 Bit 7 Word 2 ’1’ bit6 bit7 2000 Microchip Technology Inc. ...
Page 179
... RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’. 2000 Microchip Technology Inc. Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 16 ...
Page 180
... Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing bit CREN. Advanced Information 2000 Microchip Technology Inc. ...
Page 181
... RCREG USART Receive Register TXSTA CSRC TX9 TXEN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave reception. 2000 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF TXIF ...
Page 182
... PIC18CXX8 NOTES: DS30475A-page 182 Advanced Information 2000 Microchip Technology Inc. ...
Page 183
... Programmable clock source • Programmable link to timer module for time-stamping and network synchronization • Low power SLEEP mode 2000 Microchip Technology Inc. 17.1.1 OVERVIEW OF THE MODULE The CAN bus module consists of a Protocol Engine and message buffering and control. The CAN protocol engine handles all functions for receiving and transmit- ting messages on the CAN bus ...
Page 184
... Acceptance Filter RXF2 A Acceptance Filter c RXF3 c Acceptance Filter e RXF4 p t Acceptance Filter RXF5 R M Identifier Data Field Receive RXERRCNT Error Counter TXERRCNT Transmit ErrPas BusOff Error Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator RX 2000 Microchip Technology Inc. ...
Page 185
... Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 0 Unimplemented: Read as ’0’ Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. 17.2.1 CAN CONTROL AND STATUS REGISTERS This section shows the CAN Control and Status registers. R/W-0 R/W-0 R/W-0 ...
Page 186
... Value at POR DS30475A-page 186 R-0 R-0 U-0 R-0 — ICODE2 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information R-0 R-0 U-0 ICODE1 ICODE0 — bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 187
... PIR3, TXB0IF goto AccessBuffer RXB1Interrupt bcf PIR3, RXB1IF goto Accessbuffer 2000 Microchip Technology Inc. ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred ; Save CANSTAT register ; This is required to make sure that ; we use same CANSTAT value rather ...
Page 188
... Copy masked value back to TempCANCON ; Retrieve ICODE bits ; Use previously saved CANSTAT value ; to make sure same value. ; Copy ICODE bits to WIN bits. ; Copy the result to actual CANCON ; Preserve current non WIN bits ; Restore original WIN bits Advanced Information 2000 Microchip Technology Inc. ...
Page 189
... EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. R/C-0 R-0 R-0 R-0 TXBO TXBP ...
Page 190
... SID7 SID6 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information U-0 R/W-0 R/W-0 — TXPRI1 TXPRI0 bit Bit is unknown R/W-x R/W-x R/W-x SID5 SID4 SID3 bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 191
... REGISTER R/W-x R/W-x EID7 bit 7 bit 7-0 EID7:EID0: Extended Identifier bits Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. R/W-x R/W-x R/W-x SID0 — EXIDE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared ...
Page 192
... U-0 R/W-x — — DLC3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information R/W-x R/W-x R/W-x bit Bit is unknown R/W-x R/W-x R/W-x DLC2 DLC1 DLC0 bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 193
... This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus off state occurs. When the bus has 128 occurrences of 11 con- secutive recessive bits, the counter value is cleared. Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. R-0 R-0 R-0 R-0 TEC5 ...
Page 194
... Value at POR DS30475A-page 194 R/W-0 U-0 R-0 RXM0 — RXRTRRO RXB0DBEN W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information R/W-0 R-0 R/W-0 JTOFF FILHIT0 bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 195
... SID10 SID9 bit 7 bit 7-0 SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL Register). Extended Identifier bits EID28:EID21, if EXID = 1. Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. R/W-0 U-0 R-0 RXM0 — RXRTRRO W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’ ...
Page 196
... Bit is set ’0’ = Bit is cleared Advanced Information U-0 R/W-x R/W-x — EID17 EID16 bit Bit is unknown R/W-x R/W-x R/W-x EID10 EID9 EID8 bit Bit is unknown R/W-x R/W-x R/W-x EID2 EID1 EID0 bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 197
... RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 n<1 and 0<m<7) Each Receive Buffer has an array of registers. For example, Receive buffer 0 has 8 registers: RXB0D0 to RXB0D7. Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. R/W-x R/W-x R/W-x RB1 RB0 DLC3 W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 198
... Value at POR DS30475A-page 198 R-0 R-0 R-0 R-0 REC5 REC4 REC3 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advanced Information R-0 R-0 R-0 REC2 REC1 REC0 bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 199
... R/W-x R/W-x EID15 EID14 bit 7 bit 7-0 EID15:EID8: Extended Identifier Filter bits Legend Readable bit - n = Value at POR 2000 Microchip Technology Inc. R/W-x R/W-x R/W-x SID8 SID7 SID6 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared ...
Page 200
... Bit is set ’0’ = Bit is cleared Advanced Information R/W-x R/W-x R/W-x EID2 EID1 EID0 bit Bit is unknown R/W-x R/W-x R/W-x SID5 SID4 SID3 bit Bit is unknown U-0 R/W-x R/W-x — EID17 EID16 bit Bit is unknown 2000 Microchip Technology Inc. ...