PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet - Page 225

• Manufacturer Part Number: PIC18C658-I/L
• Description: IC PIC MCU OTP 16KX16 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/L

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Number Of I /o: 52
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFPAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658IL; Q1162292

17.13
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or dis-
abled. The CANINTF register contains interrupt flags.
The CANINTE register contains the enables for the 8
main interrupts. A special set of read only bits in the
CANSTAT register (ICODE bits) can be used in combi-
nation with a jump table for efficient handling of inter-
rupts.
All interrupts have one source, with the exception of the
Error Interrupt. Any of the Error Interrupt sources can
set the Error Interrupt Flag. The source of the Error
Interrupt can be determined by reading the Communi-
cation Status register COMSTAT.
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
• Receive Interrupts
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error Passive Interrupt
The Transmit related interrupts are
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error Passive Interrupt
• Bus Off Interrupt
17.13.1 INTERRUPT CODE BITS
The source of a pending interrupt is indicated in the
ICODE (interrupt code) bits. Interrupts are internally
prioritized, such that the lower the ICODE value, the
higher the interrupt priority. Once the highest priority
interrupt condition has been cleared, the code for the
next highest priority interrupt that is pending (if any),
will be reflected by the ICODE bits (see Table 17-3).
Note that only those interrupt sources that have their
associated CANINTE enable bit set will be reflected in
the ICODE bits.
TABLE 17-3:
ICODE<2:0>
2000 Microchip Technology Inc.
000
001
010
011
100
101
110
111
CAN Interrupts
ERR•WAK•TX0•TX1•TX2•RX0•RX1
ERR
ERR•WAK
ERR•WAK•TX0
ERR•WAK•TX0•TX1
ERR•WAK•TX0•TX1•TX2
ERR•WAK•TX0•TX1•TX2•RX0
ERR•WAK•TX0•TX1•TX2•RX0•RX1
ICODE<2:0> DECODE
Boolean Expression
Advanced Information
17.13.2 TRANSMIT INTERRUPT
When the Transmit Interrupt is enabled, an interrupt will
be generated when the associated transmit buffer
becomes empty and is ready to be loaded with a new
message. The TXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the TXBnIF bit to a ‘0’.
17.13.3 RECEIVE INTERRUPT
When the Receive Interrupt is enabled, an interrupt will
be generated when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving the
EOF field. The RXBnIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the RXBnIF bit to a ‘0’.
17.13.4 MESSAGE ERROR INTERRUPT
When an error occurs during transmission or reception
of a message, the message error flag IRXIF will be set
and, if the IRXIE bit is set, an interrupt will be gener-
ated. This is intended to be used to facilitate baud rate
determination when used in conjunction with Listen
Only mode.
17.13.5 BUS ACTIVITY WAKE-UP INTERRUPT
When the PIC18CXX8 is in SLEEP mode and the bus
activity wake-up interrupt is enabled, an interrupt will be
generated, and the WAKIF bit will be set, when activity
is detected on the CAN bus. This interrupt causes the
PIC18CXX8 to exit SLEEP mode. The interrupt is reset
by the MCU clearing the WAKIF bit.
PIC18CXX8
DS30475A-page 225