PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet - Page 258
![IC PIC MCU OTP 16KX16 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC18C658-I/L
Manufacturer Part Number
PIC18C658-I/L
Description
IC PIC MCU OTP 16KX16 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Number Of I /o
52
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Controller Family/series
PIC18
No. Of I/o's
52
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFPAC174007 - MODULE SKT PROMATEII 68PLCC
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C658IL
Q1162292
Q1162292
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-I/L
Manufacturer:
Microchip
Quantity:
385
Company:
Part Number:
PIC18C658-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18C658-I/L
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 258 of 366
- Download datasheet (7Mb)
PIC18CXX8
22.3.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and inter-
• If the interrupt condition occurs during or after
FIGURE 22-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT
DS30475A-page 258
Note 1:
rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
the execution of a SLEEP instruction, the device
will immediately wake-up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
INSTRUCTION FLOW
Instruction
fetched
CLKOUT
Instruction
executed
2:
3:
4:
INTIF bit
GIEH bit
INT pin
OSC1
WAKE-UP USING INTERRUPTS
PC
(4)
XT, HS or LP oscillator mode assumed.
GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE is cleared, execution will continue in-line.
T
CLKOUT is not available in these oscillator modes, but shown here for timing reference.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
OSC
(drawing not to scale). This delay will not occur for RC and EC osc modes.
Q1 Q2 Q3 Q4
Inst(PC + 2)
SLEEP
PC+2
Q1
Processor in
Advanced Information
SLEEP
PC+4
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 4)
Inst(PC + 2)
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
PC+4
Interrupt Latency
Dummy cycle
(1,2)
PC + 4
(3)
Q1 Q2 Q3 Q4
2000 Microchip Technology Inc.
Inst(0008h)
Dummy cycle
0008h
Q1 Q2 Q3 Q4
Inst(000Ah)
Inst(0008h)
000Ah
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