PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet - Page 220

• Manufacturer Part Number: PIC18C658-I/L
• Description: IC PIC MCU OTP 16KX16 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C658-I/L

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Number Of I /o: 52
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: 3-Wire, I2C, SPI, USART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163007, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFPAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C658IL; Q1162292

PIC18CXX8
17.8
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time (Sync
Seg). The circuit will then adjust the values of phase
segment 1 and phase segment 2, as necessary. There
are two mechanisms used for synchronization.
17.8.1
Hard Synchronization is only done when there is a
recessive to dominant edge during a BUS IDLE condi-
tion, indicating the start of a message. After hard syn-
chronization, the bit time counters are restarted with
Sync Seg. Hard synchronization forces the edge, which
has occurred to lie within the synchronization segment
of the restarted bit time. Due to the rules of synchroni-
zation, if a hard synchronization occurs, there will not
be a resynchronization within that bit time.
17.8.2
As a result of Resynchronization, phase segment 1
may be lengthened, or phase segment 2 may be short-
ened. The amount of lengthening or shortening of the
phase buffer segments has an upper bound given by
the Synchronization Jump Width (SJW). The value of
the SJW will be added to phase segment 1 (see
Figure 17-7), or subtracted from phase segment 2 (see
Figure 17-8). The SJW is programmable between 1 T
and 4 T
Clocking information will only be derived from reces-
sive to dominant transitions. The property that only a
fixed maximum number of successive bits have the
same value, ensures resynchronization to the bit
stream during a frame.
DS30475A-page 220
Q
Synchronization
HARD SYNCHRONIZATION
RESYNCHRONIZATION
.
Advanced Information
Q
The phase error of an edge is given by the position of
the edge relative to Sync Seg, measured in T
phase error is defined in magnitude of T
• e = 0 if the edge lies within SYNCESEG.
• e > 0 if the edge lies before the SAMPLE POINT.
• e < 0 if the edge lies after the SAMPLE POINT of
If the magnitude of the phase error is less than, or equal
to, the programmed value of the synchronization jump
width, the effect of a resynchronization is the same as
that of a hard synchronization.
If the magnitude of the phase error is larger than the
synchronization jump width, and if the phase error is
positive, then phase segment 1 is lengthened by an
amount equal to the synchronization jump width.
If the magnitude of the phase error is larger than the
resynchronization jump width, and if the phase error is
negative, then phase segment 2 is shortened by an
amount equal to the synchronization jump width.
17.8.3
• Only one synchronization within one bit time is
• An edge will be used for synchronization only if
• All other recessive to dominant edges, fulfilling
the previous bit.
allowed.
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
rules 1 and 2, will be used for resynchronization
with the exception that a node transmitting a dom-
inant bit will not perform a resynchronization, as a
result of a recessive to dominant edge with a pos-
itive phase error.
SYNCHRONIZATION RULES
2000 Microchip Technology Inc.
Q
as follows:
Q
. The