PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 9

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

2.0
2.1
The PIC12F629/675 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h-03FFh)
for the PIC12F629/675 devices is physically imple-
mented. Accessing a location above these boundaries
will cause a wrap-around within the first 1K x 14 space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 2-1).
FIGURE 2-1:
 2010 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
On-chip Program
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
PC<12:0>
Memory
PROGRAM MEMORY MAP
AND STACK FOR THE
DSTEMP/675
13
000h
0004
0005
03FFh
0400h
1FFFh
2.2
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose
Registers and the Special Function Registers. The
Special Function Registers are located in the first 32
locations of each bank. Register locations 20h-5Fh are
General Purpose Registers, implemented as static
RAM and are mapped across both banks. All other
RAM is unimplemented and returns ‘0’ when read. RP0
(STATUS<5>) is the bank select bit.
• RP0 = 0 Bank 0 is selected
• RP0 = 1 Bank 1 is selected
2.2.1
The register file is organized as 64 x 8 in the
PIC12F629/675 devices. Each register is accessed,
either directly or indirectly, through the File Select
Register FSR (see Section 2.4 “Indirect Addressing,
INDF and FSR Registers”).
Note:
Data Memory Organization
The IRP and RP1 bits STATUS<7:6> are
reserved and should always be maintained
as ‘0’s.
GENERAL PURPOSE REGISTER
FILE
PIC12F629/675
DS41190G-page 9