PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 63

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

9.4
The PIC12F629/675 has 7 sources of interrupt:
• External Interrupt GP2/INT
• TMR0 Overflow Interrupt
• GPIO Change Interrupts
• Comparator Interrupt
• A/D Interrupt (PIC12F675 only)
• TMR1 Overflow Interrupt
• EEPROM Data Write Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt register (PIR) record individual interrupt
requests in flag bits. The INTCON register also has
individual and Global Interrupt Enable (GIE) bits.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register and PIE register. GIE is cleared on
Reset.
The return from interrupt instruction,
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT pin interrupt
• GP port change interrupt
• TMR0 overflow interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in special register PIE1.
The following interrupt flags are contained in the PIR
register:
• EEPROM data write interrupt
• A/D interrupt
• Comparator interrupt
• Timer1 overflow interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt
• The return address is pushed onto the stack
• The PC is loaded with 0004h
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid GP2/
INT recursive interrupts.
For external interrupt events, such as the INT pin, or
GP port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 9-11). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
 2010 Microchip Technology Inc.
Interrupts
RETFIE
, exits
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set,
2: When an instruction that clears the GIE
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts which were
ignored are still pending to be serviced
when the GIE bit is set again.
PIC12F629/675
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DS41190G-page 63
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