PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 42

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

PIC12F629/675
REGISTER 6-2:
6.9
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The CMIE bit (PIE1<3>) and the PEIE bit (INT-
CON<6>) must be set to enable the interrupt. In addi-
tion, the GIE bit must also be set. If any of these bits are
cleared, the interrupt is not enabled, though the CMIF
bit will still be set if an interrupt condition occurs.
TABLE 6-2:
DS41190G-page 42
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
0Bh/8Bh
0Ch
19h
8Ch
85h
99h
Legend:
Address
R/W-0
VREN
Comparator Interrupts
INTCON
PIR1
CMCON
PIE1
TRISIO
VRCON
Name
x = unknown, u = unchanged, - = unimplemented, read as ‘
VREN: CV
1 = CV
0 = CV
Unimplemented: Read as ‘0’
VRR: CV
1 = Low range
0 = High range
Unimplemented: Read as ‘0’
VR3:VR0: CV
When VRR = 1: CV
When VRR = 0: CV
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
U-0
—
VREN
VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
EEIF
EEIE
Bit 7
GIE
REF
REF
—
—
REF
REF
circuit powered on
circuit powered down, no I
Range Selection bit
REF
W = Writable bit
‘1’ = Bit is set
COUT
Enable bit
PEIE
ADIF
ADIE
Bit 6
—
—
R/W-0
value selection 0  VR [3:0]  15
VRR
REF
REF
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
= (VR3:VR0 / 24) * V
= V
Bit 5
T0IE
VRR
—
—
—
DD
/4 + (VR3:VR0 / 32) * V
R/W-0
CINV
Bit 4
INTE
—
—
—
—
DD
drain
GPIE
CMIF
CMIE
Bit 3
VR3
CIS
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DD
0
R/W-0
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
VR3
’. Shaded cells are not used by the comparator module.
Note:
Bit 2
CM2
T0IF
VR2
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
—
—
DD
If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
Bit 1
INTF
CM1
VR1
—
—
R/W-0
VR2
TMR1IF
TMR1IE
GPIF
Bit 0
CM0
VR0
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
0000 0000
00-- 0--0
-0-0 0000
00-- 0--0
--11 1111
0-0- 0000
POR, BOD
VR1
Value on
0000 000u
00-- 0--0
-0-0 0000
00-- 0--0
--11 1111
0-0- 0000
Value on
all other
R/W-0
Resets
VR0
bit 0