PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 49

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

8.0
The EEPROM data memory is readable and writable
during normal operation (full V
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
• EECON1
• EECON2 (not a physically implemented register)
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC12F629/675 devices have 128
bytes of data EEPROM with an address range from 0h
to 7Fh.
REGISTER 8-1:
REGISTER 8-2:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
EEDAT7
R/W-0
U-0
—
DATA EEPROM MEMORY
EEDATn: Byte value to write to or read from data EEPROM
Unimplemented: Should be set to ‘0’
EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation
EEDAT6
EADR6
R/W-0
R/W-0
EEDAT: EEPROM DATA REGISTER (ADDRESS: 9Ah)
EEADR: EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
DD
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
range). This memory
EEDAT5
EADR5
R/W-0
R/W-0
EEDAT4
EADR4
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
EEDAT3
EADR3
R/W-0
R/W-0
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC Specifications for
exact limits.
When the data memory is code-protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
this memory.
Additional information on the data EEPROM is
available in the PIC
(DS33023).
EEDAT2
EADR2
R/W-0
R/W-0
PIC12F629/675
®
Mid-Range Reference Manual,
x = Bit is unknown
x = Bit is unknown
EEDAT1
EADR1
R/W-0
R/W-0
DS41190G-page 49
EEDAT0
EADR0
R/W-0
R/W-0
bit 0
bit 0