PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 23

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

3.2.2
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
REGISTER 3-4:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1:
U-0
—
Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
INTERRUPT-ON-CHANGE
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-Change GPIO Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
U-0
—
IOC: INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
W = Writable bit
‘1’ = Bit is set
R/W-0
IOC5
R/W-0
IOC4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
IOC3
Note:
Any read or write of GPIO. This will end the
mismatch condition.
Clear the flag bit GPIF.
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
R/W-0
IOC2
PIC12F629/675
x = Bit is unknown
R/W-0
IOC1
DS41190G-page 23
R/W-0
IOC0
bit 0