PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 12

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

PIC12F629/675
TABLE 2-1:
DS41190G-page 12
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1: This is not a physical register.
Address
2: These bits are reserved and should always be maintained as ‘
3: PIC12F675 only.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCAL
WPU
IOC
VRCON
EEDATA
EEADR
EECON1
EECON2
ADRESL
ANSEL
shaded = unimplemented
— = unimplemented locations read as ‘
Name
(1)
—
—
—
—
—
—
—
—
—
—
—
—
(3)
(3)
(1)
SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Addressing this Location uses Contents of FSR to Address Data Memory
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Data EEPROM Data Register
EEPROM Control Register 2
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result
GPPU
VREN
IRP
CAL5
EEIE
Bit 7
GIE
—
—
—
—
—
—
—
—
(2)
Data EEPROM Address Register
INTEDG
ADCS2
RP1
CAL4
PEIE
ADIE
Bit 6
—
—
—
—
—
—
—
(2)
TRISIO5
ADCS1
WPU5
T0CS
CAL3
IOC5
VRR
Bit 5
T0IE
RP0
0
—
—
—
—
’, u = unchanged, x = unknown, q = value depends on condition,
Write Buffer for Upper 5 bits of Program Counter
TRISIO4
ADCS0
WPU4
T0SE
CAL2
IOC4
Bit 4
INTE
TO
—
—
—
—
TRISIO3
WRERR
ANS3
CMIE
CAL1
GPIE
IOC3
Bit 3
VR3
PSA
0
PD
—
—
’.
TRISIO2
WREN
WPU2
ANS2
CAL0
IOC2
VR2
Bit 2
T0IF
PS2
—
—
Z
TRISIO1
WPU1
ANS1
INTF
IOC1
VR1
Bit 1
POR
PS1
WR
DC
—
—
 2010 Microchip Technology Inc.
TRISIO0
TMR1IE
WPU0
ANS0
GPIF
IOC0
Bit 0
BOD
VR0
PS0
RD
—
C
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
---0 0000
0000 0000
00-- 0--0
---- --0x
1000 00--
--11 -111
--00 0000
0-0- 0000
0000 0000
-000 0000
---- x000
---- ----
xxxx xxxx
-000 1111
POR, BOD
Value on
—
—
—
—
—
—
—
—
—
—
—
—
20,61
14,31
46,61
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44
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