PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 65

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

9.4.1
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, the INTF bit (INT-
CON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from Sleep if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 9.7 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 9-13 for timing of wake-up from
Sleep through GP2/INT interrupt.
9.4.2
An overflow (FFh  00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0 “Timer0 Module”.
FIGURE 9-11:
 2010 Microchip Technology Inc.
INSTRUCTION FLOW
Note:
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF Flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
Executed
Instruction
Fetched
PC
enabled/disabled
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
GP2/INT INTERRUPT
TMR0 INTERRUPT
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3
Q1
Inst (PC - 1)
Inst (PC)
INT PIN INTERRUPT TIMING
1
Q2
PC
by
Q3
4
setting/clearing
Q4
5
Q1
Inst (PC+1)
Inst (PC)
Q2
1
PC + 1
CY
Q3
. Synchronous latency = 3 T
T0IE
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
9.4.3
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
9.4.4
See
description of comparator interrupt.
9.4.5
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
See Section 7.0 “Analog-to-Digital Converter (A/D)
Module (PIC12F675 only)” for operation of the A/D
converter interrupt.
PC + 1
—
Note:
Q3
Section 6.9
Q4
CY
2
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
, where T
GPIO INTERRUPT
COMPARATOR INTERRUPT
A/D CONVERTER INTERRUPT
Q1
Dummy Cycle
PIC12F629/675
Inst (0004h)
Q2
CY
0004h
“Comparator
= instruction cycle time. Latency
Q3
Q4
Q1
DS41190G-page 65
Interrupts”
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
for