PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 47

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PIC12F675T-I/SN

Manufacturer Part Number
PIC12F675T-I/SN
Description
IC MCU CMOS 1K FLASH W/AD 8-SOIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr

Specifications of PIC12F675T-I/SN

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
128Byte
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC12F675-I/SNTR
PIC12F675-I/SNTR
PIC12F675T-I/SN
PIC12F675T-I/SNTR
Q1324216

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12F675T-I/SN
Manufacturer:
MICROCHIP
Quantity:
44 520
Part Number:
PIC12F675T-I/SN
Manufacturer:
MICROCHIPS-PB
Quantity:
3 170
7.2
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-3. The source
impedance (R
impedance directly affect the time required to charge
the capacitor C
impedance varies over the device voltage (V
Figure 7-3. The maximum recommended imped-
ance for analog sources is 10 k. As the impedance
EQUATION 7-1:
FIGURE 7-3:
 2010 Microchip Technology Inc.
T
T
T
ACQ
ACQ
C
Note 1: The reference voltage (V
A/D Acquisition Requirements
2: The charge holding capacitor (C
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
=
=
=
=
=
=
=
=
leakage specification.
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
T
2s + T
C
- 120pF (1k + 7k + 10k) In(0.0004885)
16.47s
2s + 16.47s + [(50°C -25C)(0.05s/C)
19.72s
S
AMP
HOLD
) and the internal sampling switch (R
Legend: C
HOLD
+ T
C
(R
VA
. The sampling switch (R
C
+ [(Temperature -25°C)(0.05s/°C)]
ACQUISITION TIME
ANALOG INPUT MODEL
IC
+ T
V
I
R
SS
C
R
+ R
LEAKAGE
T
PIN
IC
HOLD
S
COFF
SS
ANx
C
5 pF
+ R
HOLD
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
S
) In(1/2047)
various junctions
) must be allowed
REF
) has no effect on the equation, since it cancels itself out.
HOLD
V
DD
DD
), see
V
V
) is not discharged after each conversion.
T
T
SS
SS
= 0.6V
= 0.6V
)
)
I
± 500 nA
LEAKAGE
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To
Equation 7-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D).
The 1/2 LSb error is the maximum error allowed for
the A/D to meet its specified resolution.
To calculate the minimum acquisition time, T
the PIC
R
IC
 1K
calculate
®
Mid-Range Reference Manual (DS33023).
V
SS R
Sampling
Switch
DD
6V
5V
4V
3V
2V
PIC12F629/675
SS
the
Sampling Switch
5 6 7 8 9 10 11
V
minimum
SS
C
= DAC capacitance
= 120 pF
(k)
HOLD
acquisition
DS41190G-page 47
ACQ
time,
, see

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