PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 48

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

PIC12F629/675
7.3
The A/D converter module can operate during Sleep.
This requires the A/D clock source to be set to the
internal RC oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from Sleep. If
the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
TABLE 7-2:
DS41190G-page 48
05h
0Bh, 8Bh INTCON
0Ch
1Eh
1Fh
85h
8Ch
9Eh
9Fh
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘
Address
A/D Operation During Sleep
GPIO
PIR1
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
ADCON0
TRISIO
PIE1
ADRESL
ANSEL
Name
SUMMARY OF A/D REGISTERS
Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
ADFM
Bit 7
EEIF
EEIE
GIE
—
—
—
ADCS2
VCFG
PEIE
ADIF
ADIE
Bit 6
—
—
TRISIO5
ADCS1
GPIO5
Bit 5
T0IE
—
—
—
TRISIO4
ADCS0
GPIO4
INTE
Bit 4
—
—
—
TRISIO3
0
GPIO3
CHS1
ANS3
CMIF
CMIE
GPIE
Bit 3
’. Shaded cells are not used for A/D converter module.
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.4
A device Reset forces all registers to their Reset state.
Thus the A/D module is turned off and any pending
conversion
registers are unchanged.
TRISIO2 TRISIO1 TRISIO0
GPIO2
CHS0
ANS2
Bit 2
T0IF
—
—
Effects of Reset
is
GPIO1
ANS1
Bit 1
INTF
GO
—
—
aborted.
TMR1IF
TMR1IE
GPIO0
ADON
ANS0
 2010 Microchip Technology Inc.
GPIF
Bit 0
The
--xx xxxx
0000 0000
00-- 0--0
xxxx xxxx
00-- 0000
--11 1111
00-- 0--0
xxxx xxxx
-000 1111
Value on
POR,
BOD
ADRESH:ADRESL
--uu uuuu
0000 000u
00-- 0--0
uuuu uuuu
00-- 0000
--11 1111
00-- 0--0
uuuu uuuu
-000 1111
Value on
all other
Resets