PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet - Page 59

• Manufacturer Part Number: PIC12F675T-I/SN
• Description: IC MCU CMOS 1K FLASH W/AD 8-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F675T-I/SN

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC12F675-I/SNTR; PIC12F675-I/SNTR; PIC12F675T-I/SN; PIC12F675T-I/SNTR; Q1324216

9.3.5
The PIC12F629/675 members have on-chip Brown-out
Detect circuitry. A Configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If V
greater than parameter (T
Section 12.0
Brown-out situation will reset the device. This will occur
regardless of V
to occur if V
(T
FIGURE 9-6:
9.3.6
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 9-7, Figure 9-8 and Figure 9-9 depict time-
out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-8). This is useful for testing purposes or
to synchronize more than one PIC12F629/675 device
operating in parallel.
Table 9-6 shows the Reset conditions for some special
registers, while Table 9-7 shows the Reset conditions
for all the registers.
 2010 Microchip Technology Inc.
BOD
Note 1: 72 ms delay only if PWRTE bit is programmed to ‘
).
DD
TIME-OUT SEQUENCE
BROWN-OUT DETECT (BOD)
falls below V
DD
Internal
Internal
Internal
“Electrical
Reset
Reset
Reset
slew-rate. A Reset is not guaranteed
V
V
V
DD
DD
DD
BROWN-OUT SITUATIONS
BOD
BOD
Specifications”),
DD
for less than parameter
) in Table 12-4 (see
falls below V
BOD
the
for
<72 ms
0
72 ms
’.
On any Reset (Power-on, Brown-out, Watchdog, etc.),
the chip will remain in Reset until V
BV
be invoked, if enabled, and will keep the chip in Reset
an additional 72 ms.
If V
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once V
rises above BV
72 ms Reset.
9.3.7
The power CONTROL/STATUS register, PCON
(address 8Eh) has two bits.
Bit 0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating that
a brown-out has occurred. The BOD Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration Word).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (i.e., V
have gone too low).
(1)
Note:
DD
72 ms
72 ms
DD
(see Figure 9-6). The Power-up Timer will now
drops below BV
(1)
(1)
A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
Configuration Word is set.
POWER CONTROL (PCON) STATUS
REGISTER
DD
PIC12F629/675
, the Power-up Timer will execute a
DD
while the Power-up Timer is
V
V
V
BOD
BOD
BOD
DS41190G-page 59
DD
rises above
DD
may
DD