PIC12F675T-I/SN Microchip Technology, PIC12F675T-I/SN Datasheet

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PIC12F675T-I/SN

Manufacturer Part Number
PIC12F675T-I/SN
Description
IC MCU CMOS 1K FLASH W/AD 8-SOIC
Manufacturer
Microchip Technology
Series
PIC® 12Fr

Specifications of PIC12F675T-I/SN

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
128Byte
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC12F675-I/SNTR
PIC12F675-I/SNTR
PIC12F675T-I/SN
PIC12F675T-I/SNTR
Q1324216

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PIC12F629/675
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
 2010 Microchip Technology Inc.
DS41190G

Related parts for PIC12F675T-I/SN

PIC12F675T-I/SN Summary of contents

Page 1

... Microchip Technology Inc. PIC12F629/675 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41190G ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... PIC12F675 1024 * 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.  2010 Microchip Technology Inc. PIC12F629/675 Low-Power Features: • Standby Current 2.0V, typical • Operating Current: - 8.5  ...

Page 4

... PIC12F629/675 Pin Diagrams 8-pin PDIP, SOIC, DFN-S, DFN GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/V GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/V DS41190G-page GP0/CIN+/ICSPDAT 2 7 GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT GP0/AN0/CIN+/ICSPDAT 3 6 GP1/AN1/CIN-/V REF 4 5 GP2/AN2/T0CKI/INT/COUT PP /ICSPCLK  2010 Microchip Technology Inc. ...

Page 5

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010 Microchip Technology Inc. PIC12F629/675 DS41190G-page 5 ...

Page 6

... PIC12F629/675 NOTES: DS41190G-page 6  2010 Microchip Technology Inc. ...

Page 7

... V REF AN0 AN1 AN2 AN3 Note 1: Higher order bits are from STATUS register.  2010 Microchip Technology Inc. PIC12F629/675 Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC12F629 and PIC12F675 devices are covered by this Data Sheet ...

Page 8

... AN A/D Channel 3 input ST TMR1 gate XTAL Crystal/resonator CMOS F /4 output OSC TTL CMOS Bidirectional I/O w/ programmable pull-up and interrupt-on-change ST TMR1 clock XTAL Crystal/resonator ST External clock input/RC oscillator connection Power Ground reference Power Positive supply Description  2010 Microchip Technology Inc. ...

Page 9

... Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory  2010 Microchip Technology Inc. 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers and the Special Function Registers. The Special Function Registers are located in the first 32 locations of each bank ...

Page 10

... General Purpose accesses Registers 20h-5Fh 64 Bytes 5Fh 60h 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘ 1: Not a physical register. 2: PIC12F675 only.  2010 Microchip Technology Inc. File Address (1) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah ...

Page 11

... ADCON0 ADFM VCFG Legend: — = unimplemented locations read as ‘ shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘ 3: PIC12F675 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 (2) RP0 TO PD GPIO5 ...

Page 12

... WPU1 WPU0 --11 -111 IOC1 IOC0 --00 0000 — — VR1 VR0 0-0- 0000 0000 0000 -000 0000 WR RD ---- x000 ---- ---- xxxx xxxx ANS1 ANS0 46,61 -000 1111  2010 Microchip Technology Inc — — — — — 18 — 18 — — — — — ...

Page 13

... For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  2010 Microchip Technology Inc. PIC12F629/675 For example, CLRF STATUS will clear the upper three bits and set the Z bit ...

Page 14

... PSA bit to ‘1’ (OPTION<3>). See Section 4.4 “Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 128 256 1 : 128 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 15

... IOC register must also be enabled to enable an interrupt-on-change. 2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized before clearing T0IF bit.  2010 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 16

... Disables the TMR1 overflow interrupt DS41190G-page 16 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 R/W-0 U-0 CMIE — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 R/W-0 TMR1IE — bit Bit is unknown ...

Page 17

... Unimplemented: Read as ‘0’ bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow  2010 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 18

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CAL2 CAL1 CAL0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-x POR BOD bit Bit is unknown U-0 U-0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 19

... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note, “Implementing a Table Read” (AN556).  2010 Microchip Technology Inc. PIC12F629/675 2.3.2 STACK The PIC12F629/675 family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1) ...

Page 20

... Not Used Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing ( FSR Register Location Select 1FFh  2010 Microchip Technology Inc. ...

Page 21

... GPIO<5:0>: General Purpose I/O pin 1 = Port pin is > Port pin is <V IL  2010 Microchip Technology Inc. PIC12F629/675 register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. Note: The ANSEL (9Fh) and CMCON (19h) ...

Page 22

... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 U-0 R/W-1 WPU4 — WPU2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TRISIO1 TRISIO0 bit Bit is unknown R/W-1 R/W-1 WPU1 WPU0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 23

... Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.  2010 Microchip Technology Inc. PIC12F629/675 This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of GPIO ...

Page 24

... FIGURE 3-1: BLOCK DIAGRAM OF GP0 AND GP1 PINS Analog Input Mode Data Bus WPU GPPU RD WPU PORT TRISIO Analog Input Mode RD TRISIO RD PORT IOC EN RD IOC Interrupt-on-Change RD PORT To Comparator To A/D Converter  2010 Microchip Technology Inc Weak V DD I/O pin V SS ...

Page 25

... IOC Q EN Interrupt-on-Change RD PORT To TMR0 To INT To A/D Converter  2010 Microchip Technology Inc. 3.3.4 GP3/MCLR/V Figure 3-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: ...

Page 26

... IOC Interrupt-on-Change To TMR1 or CLKGEN Note 1: Timer1 LP Oscillator enabled 2: When using Timer1 with LP oscillator, the Schmitt Trigger is by-passed. BLOCK DIAGRAM OF GP5 INTOSC Mode (1) TMR1LPEN V DD Weak GPPU Oscillator Circuit OSC2 V DD I/O pin V SS INTOSC Mode ( PORT  2010 Microchip Technology Inc. ...

Page 27

... WPU — — 96h IOC — — 9Fh ANSEL — ADCS2 Legend unknown unchanged unimplemented locations read as ‘  2010 Microchip Technology Inc. PIC12F629/675 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GP5 GP4 GP3 GP2 GP1 T0IE INTE GPIE T0IF INTF — ...

Page 28

... PIC12F629/675 NOTES: DS41190G-page 28  2010 Microchip Technology Inc. ...

Page 29

... Watchdog Timer WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.  2010 Microchip Technology Inc. Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined ...

Page 30

... The ANSEL register is defined for the (and OSC PIC12F675. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 128 256 1 : 128 OSC R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 31

... OPTION_REG GPPU INTEDG 85h TRISIO — — Legend: — = Unimplemented locations, read as ‘ Shaded cells are not used by the Timer0 module.  2010 Microchip Technology Inc. PIC12F629/675 EXAMPLE 4-1: BCF STATUS,RP0 CLRWDT CLRF TMR0 BSF STATUS,RP0 MOVLW b’00101111’ ;Required if desired ...

Page 32

... Timer1 module. Note: Additional information on timer modules is available in the PIC ence Manual, (DS33023). 0 TMR1L 1 T1SYNC 1 Prescaler OSC 0 Internal Clock 2 T1CKPS<1:0> TMR1CS ® Mid-Range Refer- TMR1ON TMR1GE T1G TMR1ON TMR1GE Synchronized Clock Input Synchronize Detect Sleep Input  2010 Microchip Technology Inc. ...

Page 33

... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010 Microchip Technology Inc. PIC12F629/675 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...

Page 34

... External clock from T1OSO/T1CKI pin (on the rising edge Internal clock (F OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 DS41190G-page 34 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 35

... TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu 8Ch PIE1 EEIE ADIE Legend unknown unchanged unimplemented, read as ‘  2010 Microchip Technology Inc. 5.5 Timer1 Oscillator A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated kHz ...

Page 36

... PIC12F629/675 NOTES: DS41190G-page 36  2010 Microchip Technology Inc. ...

Page 37

... connects to CIN- IN bit 2-0 CM2:CM0: Comparator Mode bits Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings  2010 Microchip Technology Inc. PIC12F629/675 The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator. R/W-0 R/W-0 R/W-0 ...

Page 38

... Table 6-1. DS41190G-page 38 TABLE 6-1: OUTPUT STATE VS. INPUT CONDITIONS Input Conditions + is less > < > < FIGURE 6- Output Note: CINV bit (CMCON<4>) is clear. CINV COUT SINGLE COMPARATOR + Output –  2010 Microchip Technology Inc. ...

Page 39

... REF Comparator with Output CM2:CM0 = 001 GP1/CIN- A GP0/CIN+ A GP2/COUT Analog Input, ports always reads ‘0’ Digital Input CIS = Comparator Input Switch (CMCON<3>)  2010 Microchip Technology Inc. Comparator Off (Lowest power) CM2:CM0 = 111 GP1/CIN Off (Read as ‘ ’) GP0/CIN+ D GP2/COUT D ...

Page 40

... TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified CINV CMCON EN Reset impedance of 10 k GP0/CIN+ GP1/CIN- CV REF CM2:CM0  2010 Microchip Technology Inc. ...

Page 41

... To minimize power consumption while in Sleep mode, turn off the comparator, CM2:CM0 = 111, and voltage refer- ence, VRCON<7>  2010 Microchip Technology Inc. PIC12F629/675 The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range): CV ...

Page 42

... Bit is unknown Value on Value on Bit 0 all other POR, BOD Resets GPIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 CM0 -0-0 0000 -0-0 0000 — TMR1IE 00-- 0--0 00-- 0--0 --11 1111 --11 1111 VR0 0-0- 0000 0-0- 0000  2010 Microchip Technology Inc. ...

Page 43

... DD applied used. The VCFG bit (ADCON0<6>) REF  2010 Microchip Technology Inc. circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference ...

Page 44

... ADRESL Bit 0 Unimplemented: Read as ‘ 0 ’ LSB Bit 0  2010 Microchip Technology Inc. ...

Page 45

... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current  2010 Microchip Technology Inc. PIC12F629/675 U-0 R/W-0 R/W-0 — ...

Page 46

... The corresponding TRISIO bit must be set to Input mode in order to allow external control of the voltage on the pin. DS41190G-page 46 R/W-0 R/W-1 R/W-1 ADCS0 ANS3 ANS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 ANS1 ANS0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 47

... sampling switch C = sample/hold capacitance (from DAC) HOLD  2010 Microchip Technology Inc. is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate Equation 7-1 may be used. This equation assumes ...

Page 48

... INTF GPIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu GO ADON 00-- 0000 00-- 0000 --11 1111 --11 1111 — TMR1IE 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu ANS1 ANS0 -000 1111 -000 1111  2010 Microchip Technology Inc. ...

Page 49

... Unimplemented: Should be set to ‘0’ bit 6-0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation  2010 Microchip Technology Inc. PIC12F629/675 The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...

Page 50

... EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence. U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared  2010 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...

Page 51

... WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.  2010 Microchip Technology Inc. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...

Page 52

... CMIF — — — WRERR WREN 0 ’ value depends upon condition. Value on all Value on Bit 1 Bit 0 other POR, BOD Resets — TMR1IF 00-- 0--0 00-- 0--0 0000 0000 0000 0000 -000 0000 -000 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ----  2010 Microchip Technology Inc. ...

Page 53

... Watchdog Timer (WDT) • Sleep • Code protection • ID Locations • In-Circuit Serial Programming  2010 Microchip Technology Inc. PIC12F629/675 The PIC12F629/675 has a Watchdog Timer that is controlled by Configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up ...

Page 54

... See PIC12F629/675 Programming Specification for more information. R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CPD CP BODEN MCLRE PWRTE U = Unimplemented bit, read as ‘0’ bit is cleared x = bit is unknown (1) (2) (4) (5) DD R/P-1 R/P-1 R/P-1 R/P-1 WDTE F0SC2 F0SC1 F0SC0 bit 0  2010 Microchip Technology Inc. ...

Page 55

... A series resistor may be required for AT strip cut crystals varies with the Oscillator mode selected (Approx. value = 10 M  2010 Microchip Technology Inc. FIGURE 9-2: Clock from External System Open Note 1: Functions as GP4 in EC Osc mode. TABLE 9-1: ® ...

Page 56

... OSCILLATOR Z /4. OSC Calibrating the Internal Oscillator CALIBRATING THE INTERNAL OSCILLATOR STATUS, RP0 ;Bank 1 3FFh ;Get the cal value OSCCAL ;Calibrate STATUS, RP0 ;Bank 0 /4) is output on the OSC /4 can be used for test OSC  2010 Microchip Technology Inc. DD ...

Page 57

... Ripple Counter RC OSC Note 1: This is a separate oscillator from the INTOSC/EC oscillator.  2010 Microchip Technology Inc. PIC12F629/675 They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations as indicated in Table 9-4 ...

Page 58

... OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from Sleep  2010 Microchip Technology Inc. ...

Page 59

... Table 9-6 shows the Reset conditions for some special registers, while Table 9-7 shows the Reset conditions for all the registers.  2010 Microchip Technology Inc. PIC12F629/675 On any Reset (Power-on, Brown-out, Watchdog, etc.), the chip will remain in Reset until V BV (see Figure 9-6) ...

Page 60

... uuu1 0uuu Wake-up from Sleep PWRTE = 1 1024•T 1024•T OSC OSC — — Value on all Value on Bit 0 other POR, BOD (1) Resets C 0001 1xxx 000q quuu BOD ---- --0x ---- --uq PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu  2010 Microchip Technology Inc. ...

Page 61

... Comparator input changing, bit Timer1 rolling over, bit All other interrupts generating a wake-up will cause these bits Reset was due to brown-out, then bit All other Resets will cause bit  2010 Microchip Technology Inc. • MCLR Reset during normal operation • MCLR Reset during Sleep • ...

Page 62

... MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS41190G-page 62 T PWRT T OST T PWRT T OST DD T PWRT T OST  2010 Microchip Technology Inc. ): CASE CASE ...

Page 63

... Figure 9-11). The latency is the same for one or two- cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be  2010 Microchip Technology Inc. determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests ...

Page 64

... IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE ADIF (1) ADIE EEIF EEIE Note 1: PIC12F675 only. DS41190G-page 64 T0IF Wake-up (If in Sleep mode) T0IE INTF INTE GPIF GPIE PEIE GIE  2010 Microchip Technology Inc. Interrupt to CPU ...

Page 65

... Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2010 Microchip Technology Inc. 9.4.3 GPIO INTERRUPT An input change on GPIO change sets the GPIF (INTCON< ...

Page 66

... Bit 0 other POR, BOD Resets GPIF 0000 0000 0000 000u TMR1IF 00-- 0--0 00-- 0--0 TMR1IE 00-- 0--0 00-- 0--0 instruction). During normal SLEEP and process variations from part to DD instructions clear the WDT SLEEP = Min., Temperature = Max., DD  2010 Microchip Technology Inc. ...

Page 67

... Address Name Bit 7 Bit 6 81h OPTION_REG GPPU INTEDG 2007h Config. bits CP BODEN MCLRE PWRTE WDTE Legend Unchanged, shaded cells are not used by the Watchdog Timer.  2010 Microchip Technology Inc. PIC12F629/675 1 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA Bit 5 Bit 4 ...

Page 68

... Processor in Sleep Inst( Inst( Dummy cycle instruction is being executed, the instruction. If the GIE bit is SLEEP is not desirable, the user SLEEP after the instruction. SLEEP 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h execution will continue in-line.  2010 Microchip Technology Inc. ...

Page 69

... For complete details of serial programming, please refer to the Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure 9-14.  2010 Microchip Technology Inc. PIC12F629/675 FIGURE 9-14: not been External ...

Page 70

... PIC12F629/675 NOTES: DS41190G-page 70  2010 Microchip Technology Inc. ...

Page 71

... A read operation is performed on a register even if the instruction writes to that register.  2010 Microchip Technology Inc. PIC12F629/675 For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO ...

Page 72

... Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk 1 ), the prescaler will be cleared if ® Mid-Range MCU Family Ref-  2010 Microchip Technology Inc. ...

Page 73

... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’.  2010 Microchip Technology Inc. PIC12F629/675 BCF Bit Clear f Syntax: [label] BCF f,b 0  f  127 Operands: 0  ...

Page 74

... Syntax: [label] DECF f,d 0  f  127 Operands: d  [0,1] (  (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’.  2010 Microchip Technology Inc. ...

Page 75

... Z Description: The contents of register ‘f’ are incremented. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed back in register ‘f’.  2010 Microchip Technology Inc. PIC12F629/675 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0  f  127 Operands: d  ...

Page 76

... Move label ] MOVWF f 0  f  127 (W)  (f) None Move data from W register to register ‘f’ MOVWF OPTION Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F No Operation [ label ] NOP None No operation None No operation NOP  2010 Microchip Technology Inc. ...

Page 77

... Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1  2010 Microchip Technology Inc. PIC12F629/675 RETLW Return with literal in W Syntax: [ label ] RETLW k 0  k  255 Operands: k  (W); Operation: TOS  PC Status Affected: None ...

Page 78

... Operation: (f<7:4>)  (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed in register ‘f’.  2010 Microchip Technology Inc. ...

Page 79

... Operation: Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.  2010 Microchip Technology Inc. PIC12F629/675 XORWF Exclusive OR W with f Syntax: [label] XORWF 0  f  127 Operands: d  ...

Page 80

... PIC12F629/675 NOTES: DS41190G-page 80  2010 Microchip Technology Inc. ...

Page 81

... PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits  2010 Microchip Technology Inc. 11.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

Page 82

... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility  2010 Microchip Technology Inc. ...

Page 83

... Microchip Technology Inc. 11.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip’s most cost effective high-speed hardware ...

Page 84

... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ®  2010 Microchip Technology Inc. ...

Page 85

... SS Thus, a series resistor of 50-100 pulling this pin directly to V  2010 Microchip Technology Inc. ........................................................................... -0. ) ) ...

Page 86

... FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C  T  +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41190G-page Frequency (MHz Frequency (MHz  2010 Microchip Technology Inc. ...

Page 87

... FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C  T  +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency.  2010 Microchip Technology Inc. PIC12F629/675 Frequency (MHz) 20 DS41190G-page 87 ...

Page 88

... See section on Power-on Reset for details SS 0.05* — — V/ms See section on Power-on Reset for details — 2.1 — V can be lowered in Sleep mode without losing RAM data.  +85°C for industrial A  +125°C for extended A Conditions < MHz: < F < MHz Z OSC  2010 Microchip Technology Inc. ...

Page 89

... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.  2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40C  T ...

Page 90

... I and the additional current consumed when this DD PD Conditions Note WDT, BOD, Comparators REF and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV Current REF ( Current SC (1) A/D Current  2010 Microchip Technology Inc. ...

Page 91

... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.  2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40C  T ...

Page 92

... I and the additional current consumed when this DD PD  +125C for extended Conditions Note WDT, BOD, Comparators REF and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV Current REF ( Current SC (1) A/D Current  2010 Microchip Technology Inc. ...

Page 93

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  T -40° ...

Page 94

... OSC1 pF +85°C A +125° Using EECON to read/write V = Minimum operating MIN voltage ms are violated +85°C A +85°C A +125° Minimum operating MIN voltage V ms are violated  2010 Microchip Technology Inc. ...

Page 95

... I/O port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (High-Impedance) L Low FIGURE 12-4: LOAD CONDITIONS Load Condition 1 Pin R = 464 for all pins for OSC2 output  2010 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z ...

Page 96

... INTOSC mode ns RC Osc mode ns XT Osc mode ns HS Osc mode 4/F CY OSC s LP oscillator, T L/H duty cycle OSC ns HS oscillator, T L/H duty OSC cycle ns XT oscillator, T L/H duty cycle OSC ns LP oscillator ns XT oscillator ns HS oscillator  2010 Microchip Technology Inc. ...

Page 97

... Sleep start-up time* * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. PIC12F629/675 Freq. Min Typ† ...

Page 98

... T — CY OSC New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ns (Note 1) 150 * ns 300 ns — ns — — ns —  2010 Microchip Technology Inc. ...

Page 99

... Watchdog Timer Reset I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) Reset (due to BOD) Note delay only if PWRTE bit in Configuration Word is programmed to ‘  2010 Microchip Technology Inc. PIC12F629/675 (Device not in Brown-out Detect time-out 0 ’. 34 DS41190G-page 99 ...

Page 100

... TBD ms Extended Temperature s — — 2.0 2.025 — 2.175 V TBD — — — s 100* — —  2010 Microchip Technology Inc. Conditions = 5V, -40°C to +85°C = 5V, -40°C to +85°C = OSC1 period = 5V, -40°C to +85°C  B (D005) VDD ...

Page 101

... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. PIC12F629/675 ...

Page 102

... LSb DD — V /32 — LSb DD  1/2 — — LSb 1/2* — — LSb — 2k* — — — 10* Comments V Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)  s  2010 Microchip Technology Inc. ...

Page 103

... Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module current is from External V REF 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.  2010 Microchip Technology Inc. Min Typ† Max Units — ...

Page 104

... LSb (i.e., 4 4.096V) from the last sampled voltage (as stored HOLD If the A/D clock source is selected as RC, a time added before CY the A/D clock starts. This allows the SLEEP instruction to be executed.  2010 Microchip Technology Inc. ...

Page 105

... Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.  2010 Microchip Technology Inc. ( ...

Page 106

... PIC12F629/675 NOTES: DS41190G-page 106  2010 Microchip Technology Inc. ...

Page 107

... FIGURE 13-2: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5  2010 Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline ...

Page 108

... DS41190G-page 108 OVER TEMP (+125°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (-40°C TO +25°C) DD Maximum Baseline 3.5 4 4.5 V (V) DD 125 5.0 5.5 - 5.5  2010 Microchip Technology Inc. ...

Page 109

... FIGURE 13-6: MAXIMUM I PD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5  2010 Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline ...

Page 110

... DS41190G-page 110 OVER TEMP (-40°C TO +125°C) DD Typical BOD 4 (V) DD OVER TEMP (-40°C TO +125°C) DD Typical Comparator I PD 3.0 3.5 4.0 4.5 V ( 125 5.5 - 125 5.0 5.5  2010 Microchip Technology Inc. ...

Page 111

... FIGURE 13-10: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5  2010 Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A/D I ...

Page 112

... C1 AND C2=50 pF) 1.20E-05 1.00E-05 8.00E-06 6.00E-06 4.00E-06 2.00E-06 0.00E+00 2.0 2.5 DS41190G-page 112 OVER TEMP (+125°C) DD Typical A 3 (V) DD OVER TEMP (-40°C TO +125°C), DD Typical 3.0 3.5 4.0 4.5 V (V) DD 125 5.5 - 125 5.0 5.5  2010 Microchip Technology Inc. ...

Page 113

... FIGURE 13-14: TYPICAL 2.5  2010 Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT ...

Page 114

... DS41190G-page 114 = 3.5V) DD Internal Oscillator Frequency vs Temperature 0°C 25°C 85°C Temperature (°C) Internal Oscillator Frequency 3.0V 3.5V 4.0V 4.5V V (V) DD -3sigma average +3sigma 125°C WITH 0.1  F AND 0.01  -3sigma average +3sigma 5.0V 5.5V  2010 Microchip Technology Inc. ...

Page 115

... FIGURE 13-17: TYPICAL WDT PERIOD vs 2.5  2010 Microchip Technology Inc. (-40  +125  WDT Time-out 3 3.5 4 4.5 V (V) DD PIC12F629/675 - 125 5 5.5 DS41190G-page 115 ...

Page 116

... PIC12F629/675 NOTES: DS41190G-page 116  2010 Microchip Technology Inc. ...

Page 117

... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. PIC12F629/675 Example 12F629-I /017 ...

Page 118

... PIC12F629/675 14.2 Package Details The following sections give the technical details of the packages. N NOTE DS41190G-page 118  2010 Microchip Technology Inc. ...

Page 119

... N NOTE  2010 Microchip Technology Inc φ PIC12F629/675 α c β DS41190G-page 119 ...

Page 120

... PIC12F629/675 DS41190G-page 120  2010 Microchip Technology Inc. ...

Page 121

... D N NOTE TOP VIEW A3  2010 Microchip Technology Inc. PIC12F629/675 EXPOSED PAD BOTTOM VIEW A A1 NOTE NOTE DS41190G-page 121 ...

Page 122

... PIC12F629/675 DS41190G-page 122  2010 Microchip Technology Inc. ...

Page 123

... Plastic Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. PIC12F629/675 Microchip Technology Drawing C04-131E Sheet DS41190G-page 123 ...

Page 124

... PIC12F629/675 8-Lead Plastic Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41190G-page 124 Microchip Technology Drawing C04-131E Sheet  2010 Microchip Technology Inc. ...

Page 125

... Microchip Technology Inc. PIC12F629/675 DS41190G-page 125 ...

Page 126

... PIC12F629/675 NOTES: DS41190G-page 126  2010 Microchip Technology Inc. ...

Page 127

... Updated Register 3-2; Added MD Package to the Product identification System chapter; Other minor corrections. Revision G (03/2010) Updated the Instruction Set Summary section, adding pages 76 and 77.  2010 Microchip Technology Inc. PIC12F629/675 APPENDIX B: DEVICE DIFFERENCES The differences between the PIC12F629/675 devices listed in this data sheet are shown in Table B-1. ...

Page 128

... Note: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/ or the oscillator mode may be required.  2010 Microchip Technology Inc. ® PIC12F6XX 20 MHz 1024 bytes 10-bit 64 bytes ...

Page 129

... Initializing GPIO .......................................................... 21 Saving STATUS and W Registers in RAM ................. 66 Write Verify ................................................................. 51 Code Protection .................................................................. 69 Comparator ......................................................................... 37 Associated Registers .................................................. 42 Configuration............................................................... 39 Effects of a RESET ..................................................... 41 I/O Operating Modes................................................... 39  2010 Microchip Technology Inc. PIC12F629/675 Interrupts .................................................................... 42 Operation.................................................................... 38 Operation During SLEEP............................................ 41 Output......................................................................... 40 Reference ................................................................... 41 Response Time .......................................................... 41 Comparator Specifications................................................ 102 Comparator Voltage Reference Specifications................. 102 Configuration Bits ...

Page 130

... T Time-out Sequence ............................................................ 59 Timer0................................................................................. 29 Associated Registers .................................................. 31 External Clock............................................................. 30 Interrupt ...................................................................... 29 Operation .................................................................... 29 T0CKI ......................................................................... 30 Timer1 Associated Registers .................................................. 35 Asynchronous Counter Mode ..................................... 35 Reading and Writing ........................................... 35 Interrupt ...................................................................... 33 Modes of Operations .................................................. 33 Operation During SLEEP............................................ 35 Oscillator..................................................................... 35 Prescaler .................................................................... 33 Timer1 Module with Gate Control ....................................... 32 Timing Diagrams  2010 Microchip Technology Inc. ...

Page 131

... Timing Parameter Symbology............................................. 95 TRISIO — GPIO Tri-state REGISTER (Address 85H) ............................................................................ 22 V Voltage Reference Accuracy/Error ..................................... 41 W Watchdog Timer Summary of Registers ................................................ 67 Watchdog Timer (WDT) ...................................................... 66 WPU — Weak pull-up Register (ADDRESS 95h)............................................................................. 22 WWW Address.................................................................. 133 WWW, On-Line Support ....................................................... 5  2010 Microchip Technology Inc. PIC12F629/675 DS41190G-page 131 ...

Page 132

... PIC12F629/675 NOTES: DS41190G-page 132  2010 Microchip Technology Inc. ...

Page 133

... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...

Page 134

... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41190G-page 134 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41190G  2010 Microchip Technology Inc. ...

Page 135

... Plastic Dual Flat, No Lead (4X4) (DFN) Pattern: 3-Digit Pattern Code for QTP (blank otherwise Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.  2010 Microchip Technology Inc. XXX Examples: Pattern a) b) ...

Page 136

... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350  2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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