ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 99

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note: [n] denotes input stream from 0 - 31
Note: [n] denotes input stream from 0 - 31
15 - 2
15 - 0
BC15
ST[n]
External Read/Write Address: 0340
Bit
External Read Address: 0360
Bit
Reset Value: 0000
Reset Value: 0000
15
1
0
BC14
ST[n]
15
0
14
BC15 - 0
Unused
Name
CBER
SBER
Name
ST[n]
ST[n]
ST[n]
14
0
BC13
ST[n]
13
Table 67 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only
H
H
13
0
BC12
Table 66 - BER Receiver Control Register [n] (BRCR[n]) Bits
ST[n]
12
Reserved. In normal functional mode, these bits MUST be set to zero.
Stream[n] Bit Error Rate Counter Clear: When this bit is high, it resets the internal
bit error counter and the stream BER Receiver Error Register to zero.
Stream[n] Bit Error Rate Test Start: When this bit is high, it enables the BER
receiver; starts the bit error rate test. The bit error test result is kept in the BER
Receiver Error (BRER[n]) register. Upon the completion of the BER test, set this bit to
zero. Note that the RBEREB bit must be set in the IMS Register first.
Stream[n] BER Count Bits (Read Only): The binary value of these bits refers to the
bit error counts. When it reaches its maximum value of 0xFFFF, the value will be held
and will not rollover.
H
12
0
- 037F
ST[n]
BC11
11
H
- 035F
11
0
H
BC10
ST[n]
10
H
10
0
ST[n]
BC9
9
0
9
Zarlink Semiconductor Inc.
ZL50018
8
0
ST[n]
BC8
8
99
7
0
ST[n]
BC7
7
6
0
Description
Description
ST[n]
BC6
6
5
0
ST[n]
BC5
5
4
0
ST[n]
BC4
3
0
4
ST[n]
2
0
BC3
3
CBER
ST[n]
ST[n]
1
BC2
2
SBER
ST[n]
ST[n]
BC1
Data Sheet
0
1
ST[n]
BC0
0