ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 22

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.2
The input clock for the ZL50018 can be arranged in one of three different ways. These different ways will be
explained further in Section 11.1 to Section 11.3 on page 38. Depending on the mode of operation, the input clock,
CKi, will be based on the highest data rate of either the input or both the input and output data rates. The user has
to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width of the input frame pulse and
the frequency of the input clock supplied to the device.
In Master mode and Divided Slave mode, the input clock, CKi, must be at least twice the highest input or output
data rate. For example, if the highest input data rate is 4.096 Mbps and the highest output data rate is 8.192 Mbps,
the input clock, CKi, must be 16.384 MHz, which is twice the highest overall data rate. The only exception to this is
for 16.384 Mbps input or output data. In this case, the input clock, CKi, is equal to the data rate. The input frame
pulse, FPi, must always follow CKi.
In Master mode, CKo2 and FPo2 can be programmed to be used as CKi and FPi by setting CKi_LP (bit 10) in the
Control Register (CR). This will internally loop back the CKo2 and FPo2 timing. When this bit is set, CKi and FPi
must be tied low or high externally.
In Multiplied Slave mode, the input clock, CKi, must be at least twice the highest input data rate, regardless of the
output data rate. Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi,
must be 8.192 MHz, regardless of the output data rate. The only exception to this is for 16.384 Mbps input data. In
this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi.
The ZL50018 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the
programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the
negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going
clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be
used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
16.384 Mbps or 8.192 Mbps
16.384 Mbps or 8.192 Mbps
Highest Input Data Rate
Highest Input or Output
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
4.096 Mbps
2.048 Mbps
4.096 Mbps
2.048 Mbps
Data Rate
Table 1 - CKi and FPi Configurations for Master and Divided Slave Modes
Table 2 - CKi and FPi Configurations for Multiplied Slave Mode
CKIN 1-0 Bits
CKIN 1-0 Bits
00
01
10
00
01
10
Zarlink Semiconductor Inc.
ZL50018
22
Input Clock Rate (CKi)
Input Clock Rate (CKi)
16.384 MHz
16.384 MHz
8.192 MHz
4.096 MHz
8.192 MHz
4.096 MHz
8 kHz (122 ns wide pulse)
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (244 ns wide pulse)
Input Frame Pulse (FPi)
Input Frame Pulse (FPi)
8 kHz (61 ns wide pulse)
8 kHz (61 ns wide pulse)
Data Sheet