ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 85

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1:
Note 2:
Note 3:
15 - 0
External Read/Write Addresses: 0059
Bit
Reset Value: 335C
LL[n]
15
15
The default value represents limit for 8 kHz input frequency, which is -6.4 µs (-10 UI
or programmed through the Reference Frequency Register), the following values are used instead:
’h335C (10UIp-p of 1.544 MHz i.e. 6.4 µs) - if reference frequency is 8 kHz
’h0055 (0.3UIp-p) - if reference frequency is 1.544 MHz
’h003B (0.2UIp-p) - if reference frequency is 2.048 MHz
’h001E (0.2UIp-p) - if reference frequency is 4.096 MHz
’h000F (0.2UIp-p) - if reference frequency is 8.192 MHz
’h0008 (0.2UIp-p) - if reference frequency is 16.384 MHz
’h0007 (0.2UIp-p) - if reference frequency is 19.44 MHz
The name ‘lower’ is based on frequency.
When the MRLE bit of DPLLCR register is low, these registers are ignored. Depending on reference frequency (detected
LL[n]
14
14
LL[n]15 - 0
(n = 0 to 3)
Name
LL[n]
13
13
H
(see Note 1)
LL[n]
12
Reference n Single Period Lower Limit Bits: The binary value of these bits defines the
lower limit for the period of the REFn input, minus 1. The unit of the binary value is
measured in 100 MHz clock periods.
12
Table 53 - Lower Limit Register (RnLLR) Bits, (n = 0 - 3)
LL[n]
11
11
H
, 005D
LL[n]
10
10
H
, 0061
LL[n]
H
Zarlink Semiconductor Inc.
9
9
, 0065
ZL50018
LL[n]
H
8
8
85
LL[n]
7
7
Description
LL[n]
6
6
LL[n]
5
5
LL[n]
4
4
p-p
of 1.544 MHz).
LL[n]
3
3
LL[n]
2
2
Data Sheet
LL[n]
1
1
LL[n]
0
0