ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 30

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.2
In addition to the input bit delay feature, the ZL50018 allows users to change the sampling point of the input bit by
programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 31 (SICR0 - 31). For input
streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the
sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. When the stream is operating at 16.384 Mbps, the default
sampling point is 1/2 bit and can be adjusted to a 4/4 bit position.
STi[n]
STIN[n]SMP1-0 = 00
2, 4 or 8 Mbps - Default
FPi
STi[n]
STIN[n]SMP1-0 = 01
(2, 4 or 8 Mbps)
STi[n]
STIN[n]SMP1-0 = 10
2, 4 or 8 Mbps
STIN[n]SMP1-0 = 00
16Mbps - Default
STi[n]
STIN[n]SMP1-0 = 11
2, 4 or 8 Mbps
STIN[n]SMP1-0 = 10
16Mbps
Input Bit Sampling Point Programming
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively.
2
Last Channel
Figure 14 - Input Bit Sampling Point Programming
2
1
Last Channel
Last Channel
Last Channel
1
1
1
Zarlink Semiconductor Inc.
0
ZL50018
0
30
0
0
7
7
7
Sampling Point = 1/4 Bit
7
Sampling Point = 1/2 Bit
6
Sampling Point = 3/4 Bit
6
Sampling Point = 4/4 Bit
Channel 0
Channel 0
Channel 0
Channel 0
6
6
5
5
5
5
Data Sheet