ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 66

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Reset Value: 0000
External Read/Write Address: 0040
15
0
Bit
4
3
2
1
0
14
0
DPLL_
Name
MRLE
RFRE
SWF
SWE
IRM
H
13
0
12
0
Table 29 - DPLL Control Register (DPLLCR) Bits (continued)
Software Mode Fast Control Bit. When this bit is low, the SWE bit is high, and the
DPLL is in freerun mode (the FDM1 - 0 bits of the RCCR register are =’11’), the software
slow control mode is enabled. The DPLL outputs will stabilize to delta frequency contents
of Software Delta Frequency Register (SWDFR), after programmed internal DPLL filter
response and phase alignment speed (phase slope) time.
When this bit is high, the SWE bit is high, and the DPLL is in freerun mode, the software
fast control mode is enabled. The DPLL outputs will reach the delta frequency contents
of Software Delta Frequency Register (SWDFR), immediately after writing to the
Software Delta Frequency Register, therefore allowing external software filters and
phase alignment speed (phase slope) limiters to be used. This case will usually require
very frequent updating of the SWDFR register.
When the SWE bit is low or the DPLL is not in freerun mode, this bit is ignored.
Software Mode Enable Bit. When this bit is low, the Software Delta Frequency Register
(SWDFR) content is ignored and the software mode of the DPLL is disabled. When this
bit is high and the DPLL is in freerun mode, the DPLL software mode is enabled,
meaning that the Software Delta Frequency Register content is used to control the DPLL
output frequency, depending on the value of SWF bit of this register.
When the DPLL is not in freerun mode, this bit is ignored.
Monitor Register Limits Enable Bit. When this bit is low, the monitor register content is
ignored and the Stratum 3 default value for each detected reference frequency is used to
set up the DPLL’s reference monitoring functions. When this bit is high, the monitor
registers contents are used to control the monitoring functionality of the device. The
following registers are affected: RnULR, RnLLR, RnMPCRL, RnMPCRU, MPNULRL,
MPNULRU, MPFULRL, MPFULRU, MPNLLRL, MPNLLRU, MPFLLRL, MPFLLRU.
Reference Frequency Register Enable. When this bit is low, the reference frequency
value used in the DPLL comes from appropriate reference frequency detector. When this
bit is high, the reference frequency value comes from Reference Frequency Register
(RFR).
DPLL Internal Reset Mode. When this bit is low, the DPLL module is in the operational
state. When this bit is high, the DPLL module is in the power saving mode. Registers are
not reset and are still accessible in the power saving mode.
H
11
0
10
0
9
0
Zarlink Semiconductor Inc.
ZL50018
8
0
66
LIN_
RES
7
Description
SM_
FST
6
5
0
SWF
4
SWE
3
MRLE
2
RFRE
Data Sheet
1
DPLL
_IRM
0