ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 45

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.326 ms (61 ppm). The width of the register and the limiter circuitry, if not bypassed, provide a maximum phase
change alignment speed of 186 ppm.
The limiter circuitry can be bypassed by programming BLM (bit 13) in the Bandwidth Control Register (BWCR).
Bypassing limiter (combined with choice of other parameters in the BWCR register) can achieve very fast lock of
the output clock to the selected input reference. A side effect of the bypassing limiter is manifested through much
higher intrinsic jitter. Once the bypassing is stopped, the jitter characteristics are guaranteed. The phase alignment
speed default value is 56 ppm.
15.4
If very fast locking feature (i.e., locking time in order of 1 s) is desirable, the Bandwidth Control Register (BWCR)
can be programmed to accommodate the feature for any selected corner frequency. In this mode, the DPLL’s phase
alignment speed limiter is bypassed. See Table 39, “Bandwidth Control Register (BWCR) Bits” on page 73.
Semi-fast locking mode does not bypass the internal phase alignment speed limiter, thereby maintaining phase
alignment speed. This mode can be achieved by programming the SM_FST bit in the DPLL Control Register.
In freerun mode, the DPLL does not lock to any reference. It is important that the device is not simultaneously in
freerun mode (see the RCCR Register) and fast lock mode (see the BWCR Register). Otherwise, the output frame
pulse may not be generated correctly.
15.5
The quality of the four input reference clocks is continuously monitored by the reference monitors. There are
separate reference monitor circuits for the four DPLL references. References are checked for short phase (single
period) deviations as well as for frequency (multi-period) deviations with hysteresis.
The Reference Status Register (RSR) reports the status of the reference monitors. The register bits are described
in Table 57 on page 88. The Reference Mask Register (RMR) allows users to ignore the monitoring features of the
reference monitors. See Table 58 on page 89 for details.
15.6
Values for short phase deviations (upper and lower limit) are programmable through registers. The unit of the binary
values of these numbers is 100 MHz clock period (10 ns). Single period deviation limits are more relaxed than multi
period limits, and are used for early detection of the reference loss, or huge phase jumps.
Registers containing the lower and upper limits of the acceptance range for the single input reference period
measurement are: Reference Lower Limit Registers: R0LLR, R1LLR, R2LLR and R3LLR and the Reference Upper
Limit Registers: R0ULR, R1ULR, R2ULR and R3ULR.
The default values for the upper and lower limits are shown in the following table:
Fast Locking Mode
Reference Monitoring
Single Period Reference Monitoring
Table 11 - Values for Single Period Limits
16.384 MHz
Frequency
Reference
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
19.44 MHz
8 kHz
Zarlink Semiconductor Inc.
ZL50018
45
Comment
0.3 UI p-p
0.2 UI p-p
0.2 UI p-p
0.2 UI p-p
0.2 UI p-p
0.2 UI p-p
10 UI p-p
Data Sheet