ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 43

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.2
The input frequencies of REF 0 - 3 can be automatically detected or programmed independently by the Reference
Frequency Register (RFR) if RFRE (bit 1) in the DPLL Control Register (DPLLCR) is set. The detected frequency of
the selected reference is indicated in the Reference Change Status Register (RCSR). In addition, the detected
frequencies of all four references are indicated in the Reference Frequency Status Register (RFSR). See Table 29
on page 65, Table 30 on page 67, Table 41 on page 76 and Table 59 on page 91 for the detailed bit description of
the DPLL Control Register (DPLLCR), Reference Frequency Register (RFR), Reference Change Status Register
(RCSR) and Reference Frequency Status Register (RFSR), respectively.
13.3
The DPLL generates a limited number of output signals. All signals are synchronous to each other and in the
normal operating mode, are locked to the selected input reference. The DPLL provides outputs with the following
frequencies:
13.4
The widest tolerance required for any of the given input clock frequencies is ±130 ppm for the T1 clock
(1.544 MHz). If the system clock (crystal/oscillator) accuracy is ±30 ppm, it requires a minimum pull-in range of
±160 ppm. Users who do not require the ±30 ppm freerun accuracy of the DPLL can use a ±100 ppm system clock.
Therefore the pull-in range is a minimal ±230 ppm. The pull-in range is programmable through the Frequency
Locking Range Register (FLRR) as described in Table 35 on page 71. Since the width of the register is 14 bits, the
maximum programmable pull-in range can be as high as ±372 ppm. The minimum pull-in/hold-in range required for
Stratum 3 clocks is ±4.6 ppm. The default pull-in range of this device is ±20 ppm.
Input Frequencies Selection
Output Frequencies
Pull-In/Hold-In Range (also called Locking Range)
CKo0
CKo1
CKo2
CKo3
CKo4
CKo5
FPo0
FPo1
FPo2
FPo3
FPo5
Table 10 - Generated Output Frequencies
4.096 MHz
8.192 MHz
16.384 MHz
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
1.544 MHz or 2.048 MHz
19.44 MHz
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (61 ns wide pulse)
8 kHz (122 ns, 61 ns or 30 ns wide pulse)
8 kHz (51 ns wide pulse)
Zarlink Semiconductor Inc.
ZL50018
43
Data Sheet