ZL50018 ZARLINK [Zarlink Semiconductor Inc], ZL50018 Datasheet - Page 98

• Manufacturer Part Number: ZL50018
• Description: 2 K Digital Switch with Enhanced Stratum 3 DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note: [n] denotes input stream from 0 - 31
Note: [n] denotes input stream from 0 - 31
External Read/Write Address: 0320
Reset Value: 0000
15 - 8
15 - 9
7 - 0
8 - 0
External Read/Write Address: 0300
Bit
Bit
Reset Value: 0000
15
0
15
0
14
0
14
0
BRS7 - 0
Unused
Unused
BL8 - 0
Name
Name
ST[n]
ST[n]
H
13
0
13
0
H
12
0
12
0
Table 65 - BER Receiver Length Register [n] (BRLR[n]) Bits
Table 64 - BER Receiver Start Register [n] (BRSR[n]) Bits
Reserved. In normal functional mode, these bits MUST be set to zero.
Stream[n] BER Receive Start Bits: The binary value of these bits refers to the input
channel in which the BER data starts to be compared.
Reserved. In normal functional mode, these bits MUST be set to zero.
Stream[n] BER Length Bits: The binary value of these bits refers to the number of
consecutive channels expected to receive the BER pattern. The maximum number of
BER channels is 32, 64, 128 and 256 for the data rates of 2.048 Mbps, 4.096 Mbps,
8.192 Mbps and 16.384 Mbps respectively. The minimum number of BER channels is
1. If these bits are set to zero, no BER test will be performed.
11
0
11
0
H
- 033F
H
- 031F
10
0
10
0
H
H
9
0
9
0
ST[n]
BL8
Zarlink Semiconductor Inc.
8
0
8
ZL50018
BRS7
ST[n]
ST[n]
BL7
7
7
98
BRS6
ST[n]
ST[n]
BL6
6
6
Description
Description
BRS5
ST[n]
ST[n]
BL5
5
5
BRS4
ST[n]
ST[n]
BL4
4
4
BRS3
ST[n]
ST[n]
BL3
3
3
BRS2
ST[n]
ST[n]
BL2
2
2
BRS1
ST[n]
ST[n]
BL1
1
1
Data Sheet
BRS0
ST[n]
ST[n]
BL0
0
0